rtl8211F_led_control

hc

2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc

 kernel/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
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@@ -20,6 +20,7 @@
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 #define	PCI_DEVID_OCTEONTX2_RVU_AF		0xA065
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 /* Subsystem Device ID */
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+#define PCI_SUBSYS_DEVID_98XX                  0xB100
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 #define PCI_SUBSYS_DEVID_96XX                  0xB200
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 /* PCI BAR nos */
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@@ -137,6 +138,7 @@
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 	u16		ssow;
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 	u16		cptlfs;
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 	u16		timlfs;
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+	u16		cpt1_lfs;
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 	u8		cgx_lmac;
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 	/* Block LF's MSIX vector info */
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@@ -182,6 +184,8 @@
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 	bool	cgx_in_use; /* this PF/VF using CGX? */
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 	int	cgx_users;  /* number of cgx users - used only by PFs */
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+
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+	u8	nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
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 };
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 struct nix_txsch {
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@@ -400,6 +404,16 @@
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 		(pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
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 }
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+static inline bool is_rvu_supports_nix1(struct rvu *rvu)
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+{
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+	struct pci_dev *pdev = rvu->pdev;
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+
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+	if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
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+		return true;
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+
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+	return false;
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+}
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+
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 /* Function Prototypes
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  * RVU
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  */
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@@ -420,6 +434,7 @@
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 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
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 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
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 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
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+u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
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 int rvu_get_pf(u16 pcifunc);
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 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
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 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);