rtl8211F_led_control

hc

2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc

 kernel/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
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@@ -8,6 +8,7 @@
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 #include "hnae3.h"
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 #define HCLGEVF_CMDQ_TX_TIMEOUT		30000
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+#define HCLGEVF_CMDQ_CLEAR_WAIT_TIME	200
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 #define HCLGEVF_CMDQ_RX_INVLD_B		0
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 #define HCLGEVF_CMDQ_RX_OUTVLD_B	1
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14
 
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@@ -46,9 +47,17 @@
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 enum hclgevf_cmd_return_status {
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 	HCLGEVF_CMD_EXEC_SUCCESS	= 0,
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-	HCLGEVF_CMD_NO_AUTH	= 1,
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-	HCLGEVF_CMD_NOT_EXEC	= 2,
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-	HCLGEVF_CMD_QUEUE_FULL	= 3,
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+	HCLGEVF_CMD_NO_AUTH		= 1,
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+	HCLGEVF_CMD_NOT_SUPPORTED	= 2,
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+	HCLGEVF_CMD_QUEUE_FULL		= 3,
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+	HCLGEVF_CMD_NEXT_ERR		= 4,
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+	HCLGEVF_CMD_UNEXE_ERR		= 5,
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+	HCLGEVF_CMD_PARA_ERR		= 6,
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+	HCLGEVF_CMD_RESULT_ERR		= 7,
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+	HCLGEVF_CMD_TIMEOUT		= 8,
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+	HCLGEVF_CMD_HILINK_ERR		= 9,
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+	HCLGEVF_CMD_QUEUE_ILLEGAL	= 10,
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+	HCLGEVF_CMD_INVALID		= 11,
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 };
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 enum hclgevf_cmd_status {
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@@ -83,12 +92,17 @@
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 	/* Generic command */
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 	HCLGEVF_OPC_QUERY_FW_VER	= 0x0001,
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 	HCLGEVF_OPC_QUERY_VF_RSRC	= 0x0024,
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+	HCLGEVF_OPC_QUERY_DEV_SPECS	= 0x0050,
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+
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 	/* TQP command */
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 	HCLGEVF_OPC_QUERY_TX_STATUS	= 0x0B03,
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 	HCLGEVF_OPC_QUERY_RX_STATUS	= 0x0B13,
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 	HCLGEVF_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,
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+	/* GRO command */
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+	HCLGEVF_OPC_GRO_GENERIC_CONFIG  = 0x0C10,
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 	/* RSS cmd */
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 	HCLGEVF_OPC_RSS_GENERIC_CONFIG	= 0x0D01,
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+	HCLGEVF_OPC_RSS_INPUT_TUPLE     = 0x0D02,
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 	HCLGEVF_OPC_RSS_INDIR_TABLE	= 0x0D07,
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 	HCLGEVF_OPC_RSS_TC_MODE		= 0x0D08,
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 	/* Mailbox cmd */
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@@ -130,9 +144,26 @@
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 	u8 resv;
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 };
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+enum HCLGEVF_CAP_BITS {
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+	HCLGEVF_CAP_UDP_GSO_B,
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+	HCLGEVF_CAP_QB_B,
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+	HCLGEVF_CAP_FD_FORWARD_TC_B,
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+	HCLGEVF_CAP_PTP_B,
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+	HCLGEVF_CAP_INT_QL_B,
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+	HCLGEVF_CAP_SIMPLE_BD_B,
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+	HCLGEVF_CAP_TX_PUSH_B,
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+	HCLGEVF_CAP_PHY_IMP_B,
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+	HCLGEVF_CAP_TQP_TXRX_INDEP_B,
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+	HCLGEVF_CAP_HW_PAD_B,
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+	HCLGEVF_CAP_STASH_B,
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+};
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+
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+#define HCLGEVF_QUERY_CAP_LENGTH		3
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 struct hclgevf_query_version_cmd {
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 	__le32 firmware;
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-	__le32 firmware_rsv[5];
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+	__le32 hardware;
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+	__le32 rsv;
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+	__le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
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 };
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 #define HCLGEVF_MSIX_OFT_ROCEE_S       0
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@@ -148,7 +179,14 @@
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 	__le16 rsv[7];
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 };
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-#define HCLGEVF_RSS_HASH_KEY_OFFSET	4
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+#define HCLGEVF_GRO_EN_B               0
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+struct hclgevf_cfg_gro_status_cmd {
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+	u8 gro_en;
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+	u8 rsv[23];
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+};
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+
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+#define HCLGEVF_RSS_DEFAULT_OUTPORT_B	4
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+#define HCLGEVF_RSS_HASH_KEY_OFFSET_B	4
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 #define HCLGEVF_RSS_HASH_KEY_NUM	16
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 struct hclgevf_rss_config_cmd {
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 	u8 hash_config;
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@@ -159,11 +197,11 @@
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 struct hclgevf_rss_input_tuple_cmd {
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 	u8 ipv4_tcp_en;
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 	u8 ipv4_udp_en;
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-	u8 ipv4_stcp_en;
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+	u8 ipv4_sctp_en;
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 	u8 ipv4_fragment_en;
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 	u8 ipv6_tcp_en;
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 	u8 ipv6_udp_en;
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-	u8 ipv6_stcp_en;
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+	u8 ipv6_sctp_en;
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 	u8 ipv6_fragment_en;
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 	u8 rsv[16];
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 };
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@@ -226,11 +264,27 @@
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 #define HCLGEVF_NIC_CRQ_DEPTH_REG	0x27020
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 #define HCLGEVF_NIC_CRQ_TAIL_REG	0x27024
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 #define HCLGEVF_NIC_CRQ_HEAD_REG	0x27028
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-#define HCLGEVF_NIC_CMQ_EN_B		16
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-#define HCLGEVF_NIC_CMQ_ENABLE		BIT(HCLGEVF_NIC_CMQ_EN_B)
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+
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+/* this bit indicates that the driver is ready for hardware reset */
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+#define HCLGEVF_NIC_SW_RST_RDY_B	16
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+#define HCLGEVF_NIC_SW_RST_RDY		BIT(HCLGEVF_NIC_SW_RST_RDY_B)
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+
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 #define HCLGEVF_NIC_CMQ_DESC_NUM	1024
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 #define HCLGEVF_NIC_CMQ_DESC_NUM_S	3
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 #define HCLGEVF_NIC_CMDQ_INT_SRC_REG	0x27100
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+
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+#define HCLGEVF_QUERY_DEV_SPECS_BD_NUM		4
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+
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+struct hclgevf_dev_specs_0_cmd {
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+	__le32 rsv0;
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+	__le32 mac_entry_num;
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+	__le32 mng_entry_num;
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+	__le16 rss_ind_tbl_size;
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+	__le16 rss_key_size;
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+	__le16 int_ql_max;
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+	u8 max_non_tso_bd_num;
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+	u8 rsv1[5];
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+};
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 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
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 {
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@@ -254,6 +308,7 @@
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 int hclgevf_cmd_init(struct hclgevf_dev *hdev);
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 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
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+int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
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 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
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 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,