| .. | .. |
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| 2 | 2 | // Copyright (c) 2016-2017 Hisilicon Limited. |
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| 3 | 3 | |
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| 4 | 4 | #include "hclge_main.h" |
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| 5 | +#include "hclge_dcb.h" |
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| 5 | 6 | #include "hclge_tm.h" |
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| 7 | +#include "hclge_dcb.h" |
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| 6 | 8 | #include "hnae3.h" |
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| 7 | 9 | |
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| 8 | 10 | #define BW_PERCENT 100 |
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| .. | .. |
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| 35 | 37 | } |
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| 36 | 38 | } |
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| 37 | 39 | |
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| 38 | | - return hclge_tm_prio_tc_info_update(hdev, ets->prio_tc); |
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| 40 | + hclge_tm_prio_tc_info_update(hdev, ets->prio_tc); |
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| 41 | + |
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| 42 | + return 0; |
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| 39 | 43 | } |
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| 40 | 44 | |
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| 41 | 45 | static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev, |
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| .. | .. |
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| 49 | 53 | |
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| 50 | 54 | for (i = 0; i < HNAE3_MAX_TC; i++) { |
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| 51 | 55 | ets->prio_tc[i] = hdev->tm_info.prio_tc[i]; |
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| 52 | | - ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i]; |
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| 56 | + if (i < hdev->tm_info.num_tc) |
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| 57 | + ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i]; |
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| 58 | + else |
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| 59 | + ets->tc_tx_bw[i] = 0; |
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| 53 | 60 | |
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| 54 | 61 | if (hdev->tm_info.tc_info[i].tc_sch_mode == |
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| 55 | 62 | HCLGE_SCH_MODE_SP) |
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| .. | .. |
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| 70 | 77 | return 0; |
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| 71 | 78 | } |
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| 72 | 79 | |
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| 73 | | -static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets, |
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| 74 | | - u8 *tc, bool *changed) |
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| 80 | +static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc, |
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| 81 | + u8 *prio_tc) |
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| 75 | 82 | { |
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| 76 | | - bool has_ets_tc = false; |
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| 77 | | - u32 total_ets_bw = 0; |
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| 78 | | - u8 max_tc = 0; |
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| 83 | + int i; |
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| 84 | + |
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| 85 | + if (num_tc > hdev->tc_max) { |
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| 86 | + dev_err(&hdev->pdev->dev, |
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| 87 | + "tc num checking failed, %u > tc_max(%u)\n", |
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| 88 | + num_tc, hdev->tc_max); |
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| 89 | + return -EINVAL; |
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| 90 | + } |
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| 91 | + |
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| 92 | + for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { |
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| 93 | + if (prio_tc[i] >= num_tc) { |
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| 94 | + dev_err(&hdev->pdev->dev, |
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| 95 | + "prio_tc[%d] checking failed, %u >= num_tc(%u)\n", |
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| 96 | + i, prio_tc[i], num_tc); |
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| 97 | + return -EINVAL; |
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| 98 | + } |
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| 99 | + } |
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| 100 | + |
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| 101 | + if (num_tc > hdev->vport[0].alloc_tqps) { |
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| 102 | + dev_err(&hdev->pdev->dev, |
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| 103 | + "allocated tqp checking failed, %u > tqp(%u)\n", |
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| 104 | + num_tc, hdev->vport[0].alloc_tqps); |
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| 105 | + return -EINVAL; |
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| 106 | + } |
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| 107 | + |
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| 108 | + return 0; |
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| 109 | +} |
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| 110 | + |
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| 111 | +static u8 hclge_ets_tc_changed(struct hclge_dev *hdev, struct ieee_ets *ets, |
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| 112 | + bool *changed) |
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| 113 | +{ |
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| 114 | + u8 max_tc_id = 0; |
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| 79 | 115 | u8 i; |
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| 80 | 116 | |
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| 81 | | - for (i = 0; i < HNAE3_MAX_TC; i++) { |
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| 82 | | - if (ets->prio_tc[i] >= hdev->tc_max || |
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| 83 | | - i >= hdev->tc_max) |
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| 84 | | - return -EINVAL; |
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| 85 | | - |
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| 117 | + for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { |
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| 86 | 118 | if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i]) |
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| 87 | 119 | *changed = true; |
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| 88 | 120 | |
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| 89 | | - if (ets->prio_tc[i] > max_tc) |
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| 90 | | - max_tc = ets->prio_tc[i]; |
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| 121 | + if (ets->prio_tc[i] > max_tc_id) |
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| 122 | + max_tc_id = ets->prio_tc[i]; |
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| 123 | + } |
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| 91 | 124 | |
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| 125 | + /* return max tc number, max tc id need to plus 1 */ |
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| 126 | + return max_tc_id + 1; |
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| 127 | +} |
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| 128 | + |
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| 129 | +static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev, |
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| 130 | + struct ieee_ets *ets, bool *changed, |
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| 131 | + u8 tc_num) |
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| 132 | +{ |
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| 133 | + bool has_ets_tc = false; |
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| 134 | + u32 total_ets_bw = 0; |
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| 135 | + u8 i; |
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| 136 | + |
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| 137 | + for (i = 0; i < HNAE3_MAX_TC; i++) { |
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| 92 | 138 | switch (ets->tc_tsa[i]) { |
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| 93 | 139 | case IEEE_8021QAZ_TSA_STRICT: |
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| 94 | 140 | if (hdev->tm_info.tc_info[i].tc_sch_mode != |
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| .. | .. |
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| 96 | 142 | *changed = true; |
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| 97 | 143 | break; |
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| 98 | 144 | case IEEE_8021QAZ_TSA_ETS: |
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| 145 | + if (i >= tc_num) { |
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| 146 | + dev_err(&hdev->pdev->dev, |
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| 147 | + "tc%u is disabled, cannot set ets bw\n", |
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| 148 | + i); |
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| 149 | + return -EINVAL; |
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| 150 | + } |
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| 151 | + |
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| 99 | 152 | /* The hardware will switch to sp mode if bandwidth is |
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| 100 | 153 | * 0, so limit ets bandwidth must be greater than 0. |
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| 101 | 154 | */ |
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| .. | .. |
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| 120 | 173 | if (has_ets_tc && total_ets_bw != BW_PERCENT) |
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| 121 | 174 | return -EINVAL; |
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| 122 | 175 | |
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| 123 | | - *tc = max_tc + 1; |
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| 176 | + return 0; |
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| 177 | +} |
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| 178 | + |
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| 179 | +static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets, |
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| 180 | + u8 *tc, bool *changed) |
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| 181 | +{ |
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| 182 | + u8 tc_num; |
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| 183 | + int ret; |
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| 184 | + |
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| 185 | + tc_num = hclge_ets_tc_changed(hdev, ets, changed); |
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| 186 | + |
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| 187 | + ret = hclge_dcb_common_validate(hdev, tc_num, ets->prio_tc); |
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| 188 | + if (ret) |
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| 189 | + return ret; |
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| 190 | + |
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| 191 | + ret = hclge_ets_sch_mode_validate(hdev, ets, changed, tc_num); |
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| 192 | + if (ret) |
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| 193 | + return ret; |
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| 194 | + |
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| 195 | + *tc = tc_num; |
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| 124 | 196 | if (*tc != hdev->tm_info.num_tc) |
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| 125 | 197 | *changed = true; |
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| 126 | 198 | |
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| 127 | 199 | return 0; |
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| 128 | 200 | } |
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| 129 | 201 | |
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| 130 | | -static int hclge_map_update(struct hnae3_handle *h) |
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| 202 | +static int hclge_map_update(struct hclge_dev *hdev) |
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| 131 | 203 | { |
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| 132 | | - struct hclge_vport *vport = hclge_get_vport(h); |
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| 133 | | - struct hclge_dev *hdev = vport->back; |
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| 134 | 204 | int ret; |
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| 135 | 205 | |
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| 136 | | - ret = hclge_tm_map_cfg(hdev); |
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| 206 | + ret = hclge_tm_schd_setup_hw(hdev); |
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| 137 | 207 | if (ret) |
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| 138 | 208 | return ret; |
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| 139 | 209 | |
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| 140 | | - ret = hclge_tm_schd_mode_hw(hdev); |
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| 141 | | - if (ret) |
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| 142 | | - return ret; |
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| 143 | | - |
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| 144 | | - ret = hclge_pause_setup_hw(hdev); |
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| 210 | + ret = hclge_pause_setup_hw(hdev, false); |
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| 145 | 211 | if (ret) |
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| 146 | 212 | return ret; |
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| 147 | 213 | |
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| .. | .. |
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| 177 | 243 | return 0; |
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| 178 | 244 | } |
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| 179 | 245 | |
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| 246 | +static int hclge_notify_down_uinit(struct hclge_dev *hdev) |
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| 247 | +{ |
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| 248 | + int ret; |
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| 249 | + |
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| 250 | + ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); |
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| 251 | + if (ret) |
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| 252 | + return ret; |
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| 253 | + |
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| 254 | + return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); |
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| 255 | +} |
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| 256 | + |
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| 257 | +static int hclge_notify_init_up(struct hclge_dev *hdev) |
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| 258 | +{ |
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| 259 | + int ret; |
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| 260 | + |
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| 261 | + ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT); |
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| 262 | + if (ret) |
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| 263 | + return ret; |
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| 264 | + |
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| 265 | + return hclge_notify_client(hdev, HNAE3_UP_CLIENT); |
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| 266 | +} |
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| 267 | + |
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| 180 | 268 | static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets) |
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| 181 | 269 | { |
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| 182 | 270 | struct hclge_vport *vport = hclge_get_vport(h); |
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| 271 | + struct net_device *netdev = h->kinfo.netdev; |
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| 183 | 272 | struct hclge_dev *hdev = vport->back; |
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| 184 | 273 | bool map_changed = false; |
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| 185 | 274 | u8 num_tc = 0; |
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| .. | .. |
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| 193 | 282 | if (ret) |
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| 194 | 283 | return ret; |
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| 195 | 284 | |
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| 285 | + if (map_changed) { |
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| 286 | + netif_dbg(h, drv, netdev, "set ets\n"); |
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| 287 | + |
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| 288 | + ret = hclge_notify_down_uinit(hdev); |
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| 289 | + if (ret) |
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| 290 | + return ret; |
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| 291 | + } |
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| 292 | + |
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| 196 | 293 | hclge_tm_schd_info_update(hdev, num_tc); |
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| 294 | + if (num_tc > 1) |
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| 295 | + hdev->flag |= HCLGE_FLAG_DCB_ENABLE; |
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| 296 | + else |
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| 297 | + hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; |
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| 197 | 298 | |
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| 198 | 299 | ret = hclge_ieee_ets_to_tm_info(hdev, ets); |
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| 199 | 300 | if (ret) |
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| 200 | | - return ret; |
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| 301 | + goto err_out; |
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| 201 | 302 | |
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| 202 | 303 | if (map_changed) { |
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| 304 | + ret = hclge_map_update(hdev); |
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| 305 | + if (ret) |
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| 306 | + goto err_out; |
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| 307 | + |
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| 203 | 308 | ret = hclge_client_setup_tc(hdev); |
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| 309 | + if (ret) |
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| 310 | + goto err_out; |
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| 311 | + |
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| 312 | + ret = hclge_notify_init_up(hdev); |
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| 204 | 313 | if (ret) |
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| 205 | 314 | return ret; |
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| 206 | 315 | } |
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| 207 | 316 | |
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| 208 | 317 | return hclge_tm_dwrr_cfg(hdev); |
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| 318 | + |
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| 319 | +err_out: |
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| 320 | + if (!map_changed) |
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| 321 | + return ret; |
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| 322 | + |
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| 323 | + hclge_notify_init_up(hdev); |
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| 324 | + |
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| 325 | + return ret; |
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| 209 | 326 | } |
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| 210 | 327 | |
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| 211 | 328 | static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc) |
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| .. | .. |
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| 238 | 355 | static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc) |
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| 239 | 356 | { |
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| 240 | 357 | struct hclge_vport *vport = hclge_get_vport(h); |
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| 358 | + struct net_device *netdev = h->kinfo.netdev; |
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| 241 | 359 | struct hclge_dev *hdev = vport->back; |
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| 242 | 360 | u8 i, j, pfc_map, *prio_tc; |
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| 361 | + int ret; |
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| 243 | 362 | |
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| 244 | | - if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || |
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| 245 | | - hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE) |
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| 363 | + if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)) |
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| 246 | 364 | return -EINVAL; |
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| 247 | 365 | |
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| 248 | 366 | if (pfc->pfc_en == hdev->tm_info.pfc_en) |
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| .. | .. |
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| 263 | 381 | hdev->tm_info.hw_pfc_map = pfc_map; |
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| 264 | 382 | hdev->tm_info.pfc_en = pfc->pfc_en; |
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| 265 | 383 | |
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| 266 | | - return hclge_pause_setup_hw(hdev); |
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| 384 | + netif_dbg(h, drv, netdev, |
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| 385 | + "set pfc: pfc_en=%x, pfc_map=%x, num_tc=%u\n", |
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| 386 | + pfc->pfc_en, pfc_map, hdev->tm_info.num_tc); |
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| 387 | + |
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| 388 | + hclge_tm_pfc_info_update(hdev); |
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| 389 | + |
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| 390 | + ret = hclge_pause_setup_hw(hdev, false); |
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| 391 | + if (ret) |
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| 392 | + return ret; |
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| 393 | + |
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| 394 | + ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); |
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| 395 | + if (ret) |
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| 396 | + return ret; |
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| 397 | + |
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| 398 | + ret = hclge_buffer_alloc(hdev); |
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| 399 | + if (ret) { |
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| 400 | + hclge_notify_client(hdev, HNAE3_UP_CLIENT); |
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| 401 | + return ret; |
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| 402 | + } |
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| 403 | + |
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| 404 | + return hclge_notify_client(hdev, HNAE3_UP_CLIENT); |
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| 267 | 405 | } |
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| 268 | 406 | |
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| 269 | 407 | /* DCBX configuration */ |
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| .. | .. |
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| 281 | 419 | static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode) |
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| 282 | 420 | { |
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| 283 | 421 | struct hclge_vport *vport = hclge_get_vport(h); |
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| 422 | + struct net_device *netdev = h->kinfo.netdev; |
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| 284 | 423 | struct hclge_dev *hdev = vport->back; |
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| 424 | + |
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| 425 | + netif_dbg(h, drv, netdev, "set dcbx: mode=%u\n", mode); |
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| 285 | 426 | |
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| 286 | 427 | /* No support for LLD_MANAGED modes or CEE */ |
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| 287 | 428 | if ((mode & DCB_CAP_DCBX_LLD_MANAGED) || |
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| .. | .. |
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| 304 | 445 | if (hdev->flag & HCLGE_FLAG_DCB_ENABLE) |
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| 305 | 446 | return -EINVAL; |
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| 306 | 447 | |
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| 307 | | - if (tc > hdev->tc_max) { |
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| 308 | | - dev_err(&hdev->pdev->dev, |
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| 309 | | - "setup tc failed, tc(%u) > tc_max(%u)\n", |
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| 310 | | - tc, hdev->tc_max); |
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| 448 | + ret = hclge_dcb_common_validate(hdev, tc, prio_tc); |
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| 449 | + if (ret) |
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| 311 | 450 | return -EINVAL; |
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| 312 | | - } |
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| 451 | + |
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| 452 | + ret = hclge_notify_down_uinit(hdev); |
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| 453 | + if (ret) |
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| 454 | + return ret; |
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| 313 | 455 | |
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| 314 | 456 | hclge_tm_schd_info_update(hdev, tc); |
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| 457 | + hclge_tm_prio_tc_info_update(hdev, prio_tc); |
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| 315 | 458 | |
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| 316 | | - ret = hclge_tm_prio_tc_info_update(hdev, prio_tc); |
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| 459 | + ret = hclge_tm_init_hw(hdev, false); |
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| 317 | 460 | if (ret) |
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| 318 | | - return ret; |
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| 461 | + goto err_out; |
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| 319 | 462 | |
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| 320 | | - ret = hclge_tm_init_hw(hdev); |
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| 463 | + ret = hclge_client_setup_tc(hdev); |
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| 321 | 464 | if (ret) |
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| 322 | | - return ret; |
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| 465 | + goto err_out; |
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| 323 | 466 | |
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| 324 | 467 | hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; |
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| 325 | 468 | |
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| .. | .. |
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| 328 | 471 | else |
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| 329 | 472 | hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE; |
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| 330 | 473 | |
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| 331 | | - return 0; |
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| 474 | + return hclge_notify_init_up(hdev); |
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| 475 | + |
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| 476 | +err_out: |
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| 477 | + hclge_notify_init_up(hdev); |
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| 478 | + |
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| 479 | + return ret; |
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| 332 | 480 | } |
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| 333 | 481 | |
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| 334 | 482 | static const struct hnae3_dcb_ops hns3_dcb_ops = { |
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| .. | .. |
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| 338 | 486 | .ieee_setpfc = hclge_ieee_setpfc, |
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| 339 | 487 | .getdcbx = hclge_getdcbx, |
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| 340 | 488 | .setdcbx = hclge_setdcbx, |
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| 341 | | - .map_update = hclge_map_update, |
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| 342 | 489 | .setup_tc = hclge_setup_tc, |
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| 343 | 490 | }; |
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| 344 | 491 | |
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