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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
....@@ -1,4 +1,4 @@
1
-// SPDX-License-Identifier: GPL-2.0+
1
+/* SPDX-License-Identifier: GPL-2.0+ */
22 // Copyright (c) 2016-2017 Hisilicon Limited.
33 
44 #ifndef __HNS3_ENET_H
....@@ -8,14 +8,10 @@
88 
99 #include "hnae3.h"
1010 
11
-#define HNS3_MOD_VERSION "1.0"
12
-
13
-extern const char hns3_driver_version[];
14
-
1511 enum hns3_nic_state {
1612 	HNS3_NIC_STATE_TESTING,
1713 	HNS3_NIC_STATE_RESETTING,
18
-	HNS3_NIC_STATE_REINITING,
14
+	HNS3_NIC_STATE_INITED,
1915 	HNS3_NIC_STATE_DOWN,
2016 	HNS3_NIC_STATE_DISABLED,
2117 	HNS3_NIC_STATE_REMOVING,
....@@ -42,41 +38,26 @@
4238 #define HNS3_RING_TX_RING_HEAD_REG		0x0005C
4339 #define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
4440 #define HNS3_RING_TX_RING_OFFSET_REG		0x00064
41
+#define HNS3_RING_TX_RING_EBDNUM_REG		0x00068
4542 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG	0x0006C
46
-
47
-#define HNS3_RING_PREFETCH_EN_REG		0x0007C
48
-#define HNS3_RING_CFG_VF_NUM_REG		0x00080
49
-#define HNS3_RING_ASID_REG			0x0008C
50
-#define HNS3_RING_RX_VM_REG			0x00090
51
-#define HNS3_RING_T0_BE_RST			0x00094
52
-#define HNS3_RING_COULD_BE_RST			0x00098
53
-#define HNS3_RING_WRR_WEIGHT_REG		0x0009c
54
-
55
-#define HNS3_RING_INTMSK_RXWL_REG		0x000A0
56
-#define HNS3_RING_INTSTS_RX_RING_REG		0x000A4
57
-#define HNS3_RX_RING_INT_STS_REG		0x000A8
58
-#define HNS3_RING_INTMSK_TXWL_REG		0x000AC
59
-#define HNS3_RING_INTSTS_TX_RING_REG		0x000B0
60
-#define HNS3_TX_RING_INT_STS_REG		0x000B4
61
-#define HNS3_RING_INTMSK_RX_OVERTIME_REG	0x000B8
62
-#define HNS3_RING_INTSTS_RX_OVERTIME_REG	0x000BC
63
-#define HNS3_RING_INTMSK_TX_OVERTIME_REG	0x000C4
64
-#define HNS3_RING_INTSTS_TX_OVERTIME_REG	0x000C8
65
-
66
-#define HNS3_RING_MB_CTRL_REG			0x00100
67
-#define HNS3_RING_MB_DATA_BASE_REG		0x00200
68
-
69
-#define HNS3_TX_REG_OFFSET			0x40
43
+#define HNS3_RING_TX_RING_EBD_OFFSET_REG	0x00070
44
+#define HNS3_RING_TX_RING_BD_ERR_REG		0x00074
45
+#define HNS3_RING_EN_REG			0x00090
46
+#define HNS3_RING_RX_EN_REG			0x00098
47
+#define HNS3_RING_TX_EN_REG			0x000D4
7048 
7149 #define HNS3_RX_HEAD_SIZE			256
7250 
7351 #define HNS3_TX_TIMEOUT (5 * HZ)
7452 #define HNS3_RING_NAME_LEN			16
7553 #define HNS3_BUFFER_SIZE_2048			2048
76
-#define HNS3_RING_MAX_PENDING			32768
77
-#define HNS3_RING_MIN_PENDING			8
54
+#define HNS3_RING_MAX_PENDING			32760
55
+#define HNS3_RING_MIN_PENDING			72
7856 #define HNS3_RING_BD_MULTIPLE			8
79
-#define HNS3_MAX_MTU				9728
57
+/* max frame size of mac */
58
+#define HNS3_MAC_MAX_FRAME			9728
59
+#define HNS3_MAX_MTU \
60
+	(HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
8061 
8162 #define HNS3_BD_SIZE_512_TYPE			0
8263 #define HNS3_BD_SIZE_1024_TYPE			1
....@@ -109,6 +90,10 @@
10990 #define HNS3_RXD_DOI_B				21
11091 #define HNS3_RXD_OL3E_B				22
11192 #define HNS3_RXD_OL4E_B				23
93
+#define HNS3_RXD_GRO_COUNT_S			24
94
+#define HNS3_RXD_GRO_COUNT_M			(0x3f << HNS3_RXD_GRO_COUNT_S)
95
+#define HNS3_RXD_GRO_FIXID_B			30
96
+#define HNS3_RXD_GRO_ECN_B			31
11297 
11398 #define HNS3_RXD_ODMAC_S			0
11499 #define HNS3_RXD_ODMAC_M			(0x3 << HNS3_RXD_ODMAC_S)
....@@ -135,9 +120,8 @@
135120 #define HNS3_RXD_TSIND_S			12
136121 #define HNS3_RXD_TSIND_M			(0x7 << HNS3_RXD_TSIND_S)
137122 #define HNS3_RXD_LKBK_B				15
138
-#define HNS3_RXD_HDL_S				16
139
-#define HNS3_RXD_HDL_M				(0x7ff << HNS3_RXD_HDL_S)
140
-#define HNS3_RXD_HSIND_B			31
123
+#define HNS3_RXD_GRO_SIZE_S			16
124
+#define HNS3_RXD_GRO_SIZE_M			(0x3fff << HNS3_RXD_GRO_SIZE_S)
141125 
142126 #define HNS3_TXD_L3T_S				0
143127 #define HNS3_TXD_L3T_M				(0x3 << HNS3_TXD_L3T_S)
....@@ -185,14 +169,25 @@
185169 #define HNS3_VECTOR_INITED			1
186170 
187171 #define HNS3_MAX_BD_SIZE			65535
188
-#define HNS3_MAX_BD_PER_FRAG			8
189
-#define HNS3_MAX_BD_PER_PKT			MAX_SKB_FRAGS
172
+#define HNS3_MAX_TSO_BD_NUM			63U
173
+#define HNS3_MAX_TSO_SIZE			1048576U
174
+#define HNS3_MAX_NON_TSO_SIZE			9728U
175
+
190176 
191177 #define HNS3_VECTOR_GL0_OFFSET			0x100
192178 #define HNS3_VECTOR_GL1_OFFSET			0x200
193179 #define HNS3_VECTOR_GL2_OFFSET			0x300
194180 #define HNS3_VECTOR_RL_OFFSET			0x900
195181 #define HNS3_VECTOR_RL_EN_B			6
182
+
183
+#define HNS3_RING_EN_B				0
184
+
185
+enum hns3_pkt_l2t_type {
186
+	HNS3_L2_TYPE_UNICAST,
187
+	HNS3_L2_TYPE_MULTICAST,
188
+	HNS3_L2_TYPE_BROADCAST,
189
+	HNS3_L2_TYPE_INVALID,
190
+};
196191 
197192 enum hns3_pkt_l3t_type {
198193 	HNS3_L3T_NONE,
....@@ -282,15 +277,17 @@
282277 	dma_addr_t dma; /* dma address of this desc */
283278 	void *buf;      /* cpu addr for a desc */
284279 
285
-	/* priv data for the desc, e.g. skb when use with ip stack*/
280
+	/* priv data for the desc, e.g. skb when use with ip stack */
286281 	void *priv;
287282 	u32 page_offset;
288283 	u32 length;     /* length of the buffer */
289284 
290285 	u16 reuse_flag;
286
+	u16 refill;
291287 
292
-       /* desc type, used by the ring user to mark the type of the priv data */
288
+	/* desc type, used by the ring user to mark the type of the priv data */
293289 	u16 type;
290
+	u16 pagecnt_bias;
294291 };
295292 
296293 enum hns3_pkt_l3type {
....@@ -305,11 +302,11 @@
305302 	HNS3_L3_TYPE_MAC_PAUSE,
306303 	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
307304 
308
-	/* reserved for 0xA~0xB*/
305
+	/* reserved for 0xA~0xB */
309306 
310307 	HNS3_L3_TYPE_CNM = 0xc,
311308 
312
-	/* reserved for 0xD~0xE*/
309
+	/* reserved for 0xD~0xE */
313310 
314311 	HNS3_L3_TYPE_PARSE_FAIL	= 0xf /* must be last */
315312 };
....@@ -334,7 +331,7 @@
334331 	HNS3_OL3_TYPE_IPV4_OPT = 4,
335332 	HNS3_OL3_TYPE_IPV6_EXT,
336333 
337
-	/* reserved for 0x6~0xE*/
334
+	/* reserved for 0x6~0xE */
338335 
339336 	HNS3_OL3_TYPE_PARSE_FAIL = 0xf	/* must be last */
340337 };
....@@ -347,16 +344,22 @@
347344 };
348345 
349346 struct ring_stats {
350
-	u64 io_err_cnt;
351347 	u64 sw_err_cnt;
352348 	u64 seg_pkt_cnt;
353349 	union {
354350 		struct {
355351 			u64 tx_pkts;
356352 			u64 tx_bytes;
357
-			u64 tx_err_cnt;
353
+			u64 tx_more;
358354 			u64 restart_queue;
359355 			u64 tx_busy;
356
+			u64 tx_copy;
357
+			u64 tx_vlan_err;
358
+			u64 tx_l4_proto_err;
359
+			u64 tx_l2l3l4_err;
360
+			u64 tx_tso_err;
361
+			u64 over_max_recursion;
362
+			u64 hw_limitation;
360363 		};
361364 		struct {
362365 			u64 rx_pkts;
....@@ -364,22 +367,22 @@
364367 			u64 rx_err_cnt;
365368 			u64 reuse_pg_cnt;
366369 			u64 err_pkt_len;
367
-			u64 non_vld_descs;
368370 			u64 err_bd_num;
369371 			u64 l2_err;
370372 			u64 l3l4_csum_err;
373
+			u64 rx_multicast;
374
+			u64 non_reuse_pg;
371375 		};
372376 	};
373377 };
374378 
375379 struct hns3_enet_ring {
376
-	u8 __iomem *io_base; /* base io address for the ring */
377380 	struct hns3_desc *desc; /* dma map address space */
378381 	struct hns3_desc_cb *desc_cb;
379382 	struct hns3_enet_ring *next;
380383 	struct hns3_enet_tqp_vector *tqp_vector;
381384 	struct hnae3_queue *tqp;
382
-	char ring_name[HNS3_RING_NAME_LEN];
385
+	int queue_index;
383386 	struct device *dev; /* will be used for DMA mapping of descriptors */
384387 
385388 	/* statistic */
....@@ -389,67 +392,31 @@
389392 	dma_addr_t desc_dma_addr;
390393 	u32 buf_size;       /* size for hnae_desc->addr, preset by AE */
391394 	u16 desc_num;       /* total number of desc */
392
-	u16 max_desc_num_per_pkt;
393
-	u16 max_raw_data_sz_per_desc;
394
-	u16 max_pkt_size;
395395 	int next_to_use;    /* idx of next spare desc */
396396 
397397 	/* idx of lastest sent desc, the ring is empty when equal to
398398 	 * next_to_use
399399 	 */
400400 	int next_to_clean;
401
+	union {
402
+		int last_to_use;	/* last idx used by xmit */
403
+		u32 pull_len;		/* memcpy len for current rx packet */
404
+	};
405
+	u32 frag_num;
406
+	void *va; /* first buffer address for current packet */
401407 
402408 	u32 flag;          /* ring attribute */
403
-	int irq_init_flag;
404409 
405
-	int numa_node;
406
-	cpumask_t affinity_mask;
407
-};
408
-
409
-struct hns_queue;
410
-
411
-struct hns3_nic_ring_data {
412
-	struct hns3_enet_ring *ring;
413
-	struct napi_struct napi;
414
-	int queue_index;
415
-	int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
416
-	void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
417
-	void (*fini_process)(struct hns3_nic_ring_data *);
418
-};
419
-
420
-struct hns3_nic_ops {
421
-	int (*fill_desc)(struct hns3_enet_ring *ring, void *priv,
422
-			 int size, dma_addr_t dma, int frag_end,
423
-			 enum hns_desc_type type);
424
-	int (*maybe_stop_tx)(struct sk_buff **out_skb,
425
-			     int *bnum, struct hns3_enet_ring *ring);
426
-	void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);
427
-};
410
+	int pending_buf;
411
+	struct sk_buff *skb;
412
+	struct sk_buff *tail_skb;
413
+} ____cacheline_internodealigned_in_smp;
428414 
429415 enum hns3_flow_level_range {
430416 	HNS3_FLOW_LOW = 0,
431417 	HNS3_FLOW_MID = 1,
432418 	HNS3_FLOW_HIGH = 2,
433419 	HNS3_FLOW_ULTRA = 3,
434
-};
435
-
436
-enum hns3_link_mode_bits {
437
-	HNS3_LM_FIBRE_BIT = BIT(0),
438
-	HNS3_LM_AUTONEG_BIT = BIT(1),
439
-	HNS3_LM_TP_BIT = BIT(2),
440
-	HNS3_LM_PAUSE_BIT = BIT(3),
441
-	HNS3_LM_BACKPLANE_BIT = BIT(4),
442
-	HNS3_LM_10BASET_HALF_BIT = BIT(5),
443
-	HNS3_LM_10BASET_FULL_BIT = BIT(6),
444
-	HNS3_LM_100BASET_HALF_BIT = BIT(7),
445
-	HNS3_LM_100BASET_FULL_BIT = BIT(8),
446
-	HNS3_LM_1000BASET_FULL_BIT = BIT(9),
447
-	HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
448
-	HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
449
-	HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
450
-	HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
451
-	HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
452
-	HNS3_LM_COUNT = 15
453420 };
454421 
455422 #define HNS3_INT_GL_MAX			0x1FE0
....@@ -460,8 +427,6 @@
460427 
461428 #define HNS3_INT_RL_MAX			0x00EC
462429 #define HNS3_INT_RL_ENABLE_MASK		0x40
463
-
464
-#define HNS3_INT_ADAPT_DOWN_START	100
465430 
466431 struct hns3_enet_coalesce {
467432 	u16 int_gl;
....@@ -491,56 +456,33 @@
491456 	struct hns3_enet_ring_group rx_group;
492457 	struct hns3_enet_ring_group tx_group;
493458 
459
+	cpumask_t affinity_mask;
494460 	u16 num_tqps;	/* total number of tqps in TQP vector */
461
+	struct irq_affinity_notify affinity_notify;
495462 
496463 	char name[HNAE3_INT_NAME_LEN];
497464 
498
-	/* when 0 should adjust interrupt coalesce parameter */
499
-	u8 int_adapt_down;
500465 	unsigned long last_jiffies;
501466 } ____cacheline_internodealigned_in_smp;
502467 
503
-enum hns3_udp_tnl_type {
504
-	HNS3_UDP_TNL_VXLAN,
505
-	HNS3_UDP_TNL_GENEVE,
506
-	HNS3_UDP_TNL_MAX,
507
-};
508
-
509
-struct hns3_udp_tunnel {
510
-	u16 dst_port;
511
-	int used;
512
-};
513
-
514468 struct hns3_nic_priv {
515469 	struct hnae3_handle *ae_handle;
516
-	u32 enet_ver;
517
-	u32 port_id;
518470 	struct net_device *netdev;
519471 	struct device *dev;
520
-	struct hns3_nic_ops ops;
521472 
522473 	/**
523474 	 * the cb for nic to manage the ring buffer, the first half of the
524475 	 * array is for tx_ring and vice versa for the second half
525476 	 */
526
-	struct hns3_nic_ring_data *ring_data;
477
+	struct hns3_enet_ring *ring;
527478 	struct hns3_enet_tqp_vector *tqp_vector;
528479 	u16 vector_num;
480
+	u8 max_non_tso_bd_num;
529481 
530
-	/* The most recently read link state */
531
-	int link;
532482 	u64 tx_timeout_count;
533483 
534484 	unsigned long state;
535485 
536
-	struct timer_list service_timer;
537
-
538
-	struct work_struct service_task;
539
-
540
-	struct notifier_block notifier_block;
541
-	/* Vxlan/Geneve information */
542
-	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
543
-	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
544486 	struct hns3_enet_coalesce tx_coal;
545487 	struct hns3_enet_coalesce rx_coal;
546488 };
....@@ -554,26 +496,30 @@
554496 union l4_hdr_info {
555497 	struct tcphdr *tcp;
556498 	struct udphdr *udp;
499
+	struct gre_base_hdr *gre;
557500 	unsigned char *hdr;
558501 };
559502 
560
-/* the distance between [begin, end) in a ring buffer
561
- * note: there is a unuse slot between the begin and the end
562
- */
563
-static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
564
-{
565
-	return (end - begin + ring->desc_num) % ring->desc_num;
566
-}
503
+struct hns3_hw_error_info {
504
+	enum hnae3_hw_error_type type;
505
+	const char *msg;
506
+};
567507 
568508 static inline int ring_space(struct hns3_enet_ring *ring)
569509 {
570
-	return ring->desc_num -
571
-		ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
510
+	/* This smp_load_acquire() pairs with smp_store_release() in
511
+	 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
512
+	 */
513
+	int begin = smp_load_acquire(&ring->next_to_clean);
514
+	int end = READ_ONCE(ring->next_to_use);
515
+
516
+	return ((end >= begin) ? (ring->desc_num - end + begin) :
517
+			(begin - end)) - 1;
572518 }
573519 
574
-static inline int is_ring_empty(struct hns3_enet_ring *ring)
520
+static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
575521 {
576
-	return ring->next_to_use == ring->next_to_clean;
522
+	return readl(base + reg);
577523 }
578524 
579525 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
....@@ -583,22 +529,38 @@
583529 	writel(value, reg_addr + reg);
584530 }
585531 
532
+#define hns3_read_dev(a, reg) \
533
+	hns3_read_reg((a)->io_base, (reg))
534
+
535
+static inline bool hns3_nic_resetting(struct net_device *netdev)
536
+{
537
+	struct hns3_nic_priv *priv = netdev_priv(netdev);
538
+
539
+	return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
540
+}
541
+
586542 #define hns3_write_dev(a, reg, value) \
587543 	hns3_write_reg((a)->io_base, (reg), (value))
588544 
589
-#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
590
-		(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
545
+#define ring_to_dev(ring) ((ring)->dev)
591546 
592
-#define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
547
+#define ring_to_netdev(ring)	((ring)->tqp_vector->napi.dev)
593548 
594549 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
595550 	DMA_TO_DEVICE : DMA_FROM_DEVICE)
596551 
597
-#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
552
+#define hns3_buf_size(_ring) ((_ring)->buf_size)
598553 
599
-#define hnae3_buf_size(_ring) ((_ring)->buf_size)
600
-#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
601
-#define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))
554
+static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
555
+{
556
+#if (PAGE_SIZE < 8192)
557
+	if (ring->buf_size > (PAGE_SIZE / 2))
558
+		return 1;
559
+#endif
560
+	return 0;
561
+}
562
+
563
+#define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
602564 
603565 /* iterator for handling rings in ring group */
604566 #define hns3_for_each_ring(pos, head) \
....@@ -617,11 +579,13 @@
617579 int hns3_set_channels(struct net_device *netdev,
618580 		      struct ethtool_channels *ch);
619581 
620
-bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
582
+void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
621583 int hns3_init_all_ring(struct hns3_nic_priv *priv);
622584 int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
623585 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
586
+void hns3_fini_ring(struct hns3_enet_ring *ring);
624587 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
588
+bool hns3_is_phys_func(struct pci_dev *pdev);
625589 int hns3_clean_rx_ring(
626590 		struct hns3_enet_ring *ring, int budget,
627591 		void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
....@@ -633,10 +597,18 @@
633597 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
634598 				 u32 rl_value);
635599 
600
+void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
601
+void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
602
+
636603 #ifdef CONFIG_HNS3_DCB
637604 void hns3_dcbnl_setup(struct hnae3_handle *handle);
638605 #else
639606 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
640607 #endif
641608 
609
+void hns3_dbg_init(struct hnae3_handle *handle);
610
+void hns3_dbg_uninit(struct hnae3_handle *handle);
611
+void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
612
+void hns3_dbg_unregister_debugfs(void);
613
+void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);
642614 #endif