| .. | .. |
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| 170 | 170 | t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc); |
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| 171 | 171 | } |
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| 172 | 172 | |
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| 173 | | -static bool t1_pci_intr_handler(adapter_t *adapter) |
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| 173 | +static int t1_pci_intr_handler(adapter_t *adapter) |
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| 174 | 174 | { |
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| 175 | 175 | u32 pcix_cause; |
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| 176 | 176 | |
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| .. | .. |
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| 179 | 179 | if (pcix_cause) { |
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| 180 | 180 | pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, |
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| 181 | 181 | pcix_cause); |
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| 182 | | - /* PCI errors are fatal */ |
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| 183 | | - t1_interrupts_disable(adapter); |
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| 184 | | - adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR; |
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| 185 | | - pr_alert("%s: PCI error encountered.\n", adapter->name); |
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| 186 | | - return true; |
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| 182 | + t1_fatal_err(adapter); /* PCI errors are fatal */ |
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| 187 | 183 | } |
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| 188 | | - return false; |
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| 184 | + return 0; |
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| 189 | 185 | } |
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| 190 | 186 | |
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| 191 | 187 | #ifdef CONFIG_CHELSIO_T1_1G |
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| .. | .. |
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| 214 | 210 | /* |
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| 215 | 211 | * Slow path interrupt handler for FPGAs. |
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| 216 | 212 | */ |
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| 217 | | -static irqreturn_t fpga_slow_intr(adapter_t *adapter) |
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| 213 | +static int fpga_slow_intr(adapter_t *adapter) |
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| 218 | 214 | { |
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| 219 | 215 | u32 cause = readl(adapter->regs + A_PL_CAUSE); |
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| 220 | | - irqreturn_t ret = IRQ_NONE; |
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| 221 | 216 | |
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| 222 | 217 | cause &= ~F_PL_INTR_SGE_DATA; |
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| 223 | | - if (cause & F_PL_INTR_SGE_ERR) { |
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| 224 | | - if (t1_sge_intr_error_handler(adapter->sge)) |
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| 225 | | - ret = IRQ_WAKE_THREAD; |
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| 226 | | - } |
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| 218 | + if (cause & F_PL_INTR_SGE_ERR) |
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| 219 | + t1_sge_intr_error_handler(adapter->sge); |
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| 227 | 220 | |
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| 228 | 221 | if (cause & FPGA_PCIX_INTERRUPT_GMAC) |
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| 229 | 222 | fpga_phy_intr_handler(adapter); |
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| .. | .. |
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| 238 | 231 | /* Clear TP interrupt */ |
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| 239 | 232 | writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); |
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| 240 | 233 | } |
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| 241 | | - if (cause & FPGA_PCIX_INTERRUPT_PCIX) { |
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| 242 | | - if (t1_pci_intr_handler(adapter)) |
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| 243 | | - ret = IRQ_WAKE_THREAD; |
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| 244 | | - } |
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| 234 | + if (cause & FPGA_PCIX_INTERRUPT_PCIX) |
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| 235 | + t1_pci_intr_handler(adapter); |
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| 245 | 236 | |
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| 246 | 237 | /* Clear the interrupts just processed. */ |
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| 247 | 238 | if (cause) |
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| 248 | 239 | writel(cause, adapter->regs + A_PL_CAUSE); |
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| 249 | 240 | |
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| 250 | | - if (ret != IRQ_NONE) |
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| 251 | | - return ret; |
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| 252 | | - |
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| 253 | | - return cause == 0 ? IRQ_NONE : IRQ_HANDLED; |
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| 241 | + return cause != 0; |
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| 254 | 242 | } |
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| 255 | 243 | #endif |
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| 256 | 244 | |
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| .. | .. |
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| 854 | 842 | /* |
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| 855 | 843 | * Slow path interrupt handler for ASICs. |
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| 856 | 844 | */ |
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| 857 | | -static irqreturn_t asic_slow_intr(adapter_t *adapter) |
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| 845 | +static int asic_slow_intr(adapter_t *adapter) |
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| 858 | 846 | { |
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| 859 | 847 | u32 cause = readl(adapter->regs + A_PL_CAUSE); |
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| 860 | | - irqreturn_t ret = IRQ_HANDLED; |
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| 861 | 848 | |
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| 862 | 849 | cause &= adapter->slow_intr_mask; |
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| 863 | 850 | if (!cause) |
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| 864 | | - return IRQ_NONE; |
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| 865 | | - if (cause & F_PL_INTR_SGE_ERR) { |
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| 866 | | - if (t1_sge_intr_error_handler(adapter->sge)) |
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| 867 | | - ret = IRQ_WAKE_THREAD; |
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| 868 | | - } |
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| 851 | + return 0; |
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| 852 | + if (cause & F_PL_INTR_SGE_ERR) |
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| 853 | + t1_sge_intr_error_handler(adapter->sge); |
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| 869 | 854 | if (cause & F_PL_INTR_TP) |
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| 870 | 855 | t1_tp_intr_handler(adapter->tp); |
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| 871 | 856 | if (cause & F_PL_INTR_ESPI) |
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| 872 | 857 | t1_espi_intr_handler(adapter->espi); |
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| 873 | | - if (cause & F_PL_INTR_PCIX) { |
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| 874 | | - if (t1_pci_intr_handler(adapter)) |
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| 875 | | - ret = IRQ_WAKE_THREAD; |
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| 876 | | - } |
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| 877 | | - if (cause & F_PL_INTR_EXT) { |
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| 878 | | - /* Wake the threaded interrupt to handle external interrupts as |
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| 879 | | - * we require a process context. We disable EXT interrupts in |
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| 880 | | - * the interim and let the thread reenable them when it's done. |
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| 881 | | - */ |
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| 882 | | - adapter->pending_thread_intr |= F_PL_INTR_EXT; |
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| 883 | | - adapter->slow_intr_mask &= ~F_PL_INTR_EXT; |
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| 884 | | - writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA, |
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| 885 | | - adapter->regs + A_PL_ENABLE); |
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| 886 | | - ret = IRQ_WAKE_THREAD; |
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| 887 | | - } |
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| 858 | + if (cause & F_PL_INTR_PCIX) |
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| 859 | + t1_pci_intr_handler(adapter); |
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| 860 | + if (cause & F_PL_INTR_EXT) |
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| 861 | + t1_elmer0_ext_intr(adapter); |
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| 888 | 862 | |
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| 889 | 863 | /* Clear the interrupts just processed. */ |
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| 890 | 864 | writel(cause, adapter->regs + A_PL_CAUSE); |
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| 891 | 865 | readl(adapter->regs + A_PL_CAUSE); /* flush writes */ |
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| 892 | | - return ret; |
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| 866 | + return 1; |
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| 893 | 867 | } |
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| 894 | 868 | |
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| 895 | | -irqreturn_t t1_slow_intr_handler(adapter_t *adapter) |
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| 869 | +int t1_slow_intr_handler(adapter_t *adapter) |
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| 896 | 870 | { |
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| 897 | 871 | #ifdef CONFIG_CHELSIO_T1_1G |
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| 898 | 872 | if (!t1_is_asic(adapter)) |
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