rtl8211F_led_control

hc

2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc

 kernel/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
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@@ -1,10 +1,8 @@
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-/*
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- * aQuantia Corporation Network Driver
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- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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+// SPDX-License-Identifier: GPL-2.0-only
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+/* Atlantic Network Driver
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  *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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+ * Copyright (C) 2014-2019 aQuantia Corporation
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+ * Copyright (C) 2019-2020 Marvell International Ltd.
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  */
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 /* File aq_hw_utils.c: Definitions of helper functions used across
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@@ -12,6 +10,9 @@
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  */
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11
 
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 #include "aq_hw_utils.h"
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+
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+#include <linux/io-64-nonatomic-lo-hi.h>
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+
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 #include "aq_hw.h"
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 #include "aq_nic.h"
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@@ -40,9 +41,8 @@
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 {
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 	u32 value = readl(hw->mmio + reg);
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43
 
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-	if ((~0U) == value &&
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-	    (~0U) == readl(hw->mmio +
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-			   hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr))
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+	if (value == U32_MAX &&
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+	    readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX)
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 		aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
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 	return value;
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@@ -51,6 +51,34 @@
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 void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)
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 {
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 	writel(value, hw->mmio + reg);
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+}
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+
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+/* Most of 64-bit registers are in LSW, MSW form.
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+   Counters are normally implemented by HW as latched pairs:
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+   reading LSW first locks MSW, to overcome LSW overflow
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+ */
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+u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg)
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+{
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+	u64 value = U64_MAX;
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+
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+	if (hw->aq_nic_cfg->aq_hw_caps->op64bit)
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+		value = readq(hw->mmio + reg);
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+	else
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+		value = lo_hi_readq(hw->mmio + reg);
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+
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+	if (value == U64_MAX &&
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+	    readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX)
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+		aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
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+
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+	return value;
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+}
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+
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+void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value)
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+{
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+	if (hw->aq_nic_cfg->aq_hw_caps->op64bit)
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+		writeq(value, hw->mmio + reg);
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+	else
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+		lo_hi_writeq(value, hw->mmio + reg);
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 }
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 int aq_hw_err_from_flags(struct aq_hw_s *hw)
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@@ -69,3 +97,29 @@
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 err_exit:
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 	return err;
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 }
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+
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+int aq_hw_num_tcs(struct aq_hw_s *hw)
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+{
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+	switch (hw->aq_nic_cfg->tc_mode) {
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+	case AQ_TC_MODE_8TCS:
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+		return 8;
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+	case AQ_TC_MODE_4TCS:
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+		return 4;
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+	default:
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+		break;
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+	}
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+
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+	return 1;
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+}
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+
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+int aq_hw_q_per_tc(struct aq_hw_s *hw)
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+{
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+	switch (hw->aq_nic_cfg->tc_mode) {
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+	case AQ_TC_MODE_8TCS:
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+		return 4;
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+	case AQ_TC_MODE_4TCS:
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+		return 8;
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+	default:
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+		return 4;
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+	}
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+}