rtl8211F_led_control

hc

2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc

 kernel/drivers/mfd/lpc_ich.c
..
..
@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  *  lpc_ich.c - LPC interface for Intel ICH
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  *
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@@ -10,15 +11,6 @@
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11
 
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  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
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  *  Author: Aaron Sierra <asierra@xes-inc.com>
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- *
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- *  This program is free software; you can redistribute it and/or modify
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- *  it under the terms of the GNU General Public License 2 as published
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- *  by the Free Software Foundation.
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- *
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- *  This program is distributed in the hope that it will be useful,
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- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- *  GNU General Public License for more details.
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  *
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  *  This driver supports the following I/O Controller hubs:
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  *	(See the intel documentation on http://developer.intel.com.)
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..
@@ -71,6 +63,8 @@
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 #define SPIBASE_BYT		0x54
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64
 #define SPIBASE_BYT_SZ		512
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 #define SPIBASE_BYT_EN		BIT(1)
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+#define BYT_BCR			0xfc
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+#define BYT_BCR_WPD		BIT(0)
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68
 
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 #define SPIBASE_LPT		0x3800
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 #define SPIBASE_LPT_SZ		512
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@@ -1091,12 +1085,57 @@
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 	return ret;
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 }
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1088
+static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
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+{
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+	u32 val;
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+
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+	val = readl(base + BYT_BCR);
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+	if (!(val & BYT_BCR_WPD)) {
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+		val |= BYT_BCR_WPD;
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+		writel(val, base + BYT_BCR);
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+		val = readl(base + BYT_BCR);
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+	}
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+
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+	return val & BYT_BCR_WPD;
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+}
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+
1102
+static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
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+{
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+	struct pci_dev *pdev = data;
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+	u32 bcr;
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+
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+	pci_read_config_dword(pdev, BCR, &bcr);
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+	if (!(bcr & BCR_WPD)) {
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+		bcr |= BCR_WPD;
1110
+		pci_write_config_dword(pdev, BCR, bcr);
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+		pci_read_config_dword(pdev, BCR, &bcr);
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+	}
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+
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+	return bcr & BCR_WPD;
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+}
1116
+
1117
+static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
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+{
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+	unsigned int spi = PCI_DEVFN(13, 2);
1120
+	struct pci_bus *bus = data;
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+	u32 bcr;
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+
1123
+	pci_bus_read_config_dword(bus, spi, BCR, &bcr);
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+	if (!(bcr & BCR_WPD)) {
1125
+		bcr |= BCR_WPD;
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+		pci_bus_write_config_dword(bus, spi, BCR, bcr);
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+		pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1128
+	}
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+
1130
+	return bcr & BCR_WPD;
1131
+}
1132
+
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1133
 static int lpc_ich_init_spi(struct pci_dev *dev)
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1134
 {
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 	struct lpc_ich_priv *priv = pci_get_drvdata(dev);
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 	struct resource *res = &intel_spi_res[0];
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1137
 	struct intel_spi_boardinfo *info;
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-	u32 spi_base, rcba, bcr;
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+	u32 spi_base, rcba;
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1139
 
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 	info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
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1141
 	if (!info)
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@@ -1110,6 +1149,8 @@
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 		if (spi_base & SPIBASE_BYT_EN) {
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1150
 			res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
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1151
 			res->end = res->start + SPIBASE_BYT_SZ - 1;
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+
1153
+			info->set_writeable = lpc_ich_byt_set_writeable;
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1154
 		}
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 		break;
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1156
 
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@@ -1120,8 +1161,8 @@
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 			res->start = spi_base + SPIBASE_LPT;
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 			res->end = res->start + SPIBASE_LPT_SZ - 1;
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1163
 
1123
-			pci_read_config_dword(dev, BCR, &bcr);
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-			info->writeable = !!(bcr & BCR_WPD);
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+			info->set_writeable = lpc_ich_lpt_set_writeable;
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+			info->data = dev;
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 		}
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 		break;
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1168
 
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@@ -1142,8 +1183,8 @@
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 			res->start = spi_base & 0xfffffff0;
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 			res->end = res->start + SPIBASE_APL_SZ - 1;
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1185
 
1145
-			pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1146
-			info->writeable = !!(bcr & BCR_WPD);
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+			info->set_writeable = lpc_ich_bxt_set_writeable;
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+			info->data = bus;
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1188
 		}
1148
1189
 
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 		pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);