| .. | .. |
|---|
| 34 | 34 | #ifndef _HNS_ROCE_HEM_H |
|---|
| 35 | 35 | #define _HNS_ROCE_HEM_H |
|---|
| 36 | 36 | |
|---|
| 37 | | -#define HW_SYNC_SLEEP_TIME_INTERVAL 20 |
|---|
| 38 | | -#define HW_SYNC_TIMEOUT_MSECS (25 * HW_SYNC_SLEEP_TIME_INTERVAL) |
|---|
| 39 | | -#define BT_CMD_SYNC_SHIFT 31 |
|---|
| 37 | +#define HEM_HOP_STEP_DIRECT 0xff |
|---|
| 40 | 38 | |
|---|
| 41 | 39 | enum { |
|---|
| 42 | 40 | /* MAP HEM(Hardware Entry Memory) */ |
|---|
| .. | .. |
|---|
| 73 | 71 | (type >= HEM_TYPE_MTT && hop_num == 1) || \ |
|---|
| 74 | 72 | (type >= HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0)) |
|---|
| 75 | 73 | |
|---|
| 76 | | -enum { |
|---|
| 77 | | - HNS_ROCE_HEM_PAGE_SHIFT = 12, |
|---|
| 78 | | - HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT, |
|---|
| 79 | | -}; |
|---|
| 80 | | - |
|---|
| 81 | 74 | struct hns_roce_hem_chunk { |
|---|
| 82 | 75 | struct list_head list; |
|---|
| 83 | 76 | int npages; |
|---|
| .. | .. |
|---|
| 87 | 80 | }; |
|---|
| 88 | 81 | |
|---|
| 89 | 82 | struct hns_roce_hem { |
|---|
| 90 | | - struct list_head chunk_list; |
|---|
| 91 | | - int refcount; |
|---|
| 83 | + struct list_head chunk_list; |
|---|
| 84 | + refcount_t refcount; |
|---|
| 92 | 85 | }; |
|---|
| 93 | 86 | |
|---|
| 94 | 87 | struct hns_roce_hem_iter { |
|---|
| .. | .. |
|---|
| 174 | 167 | return sg_dma_address(&iter->chunk->mem[iter->page_idx]); |
|---|
| 175 | 168 | } |
|---|
| 176 | 169 | |
|---|
| 177 | | -#endif /*_HNS_ROCE_HEM_H*/ |
|---|
| 170 | +#endif /* _HNS_ROCE_HEM_H */ |
|---|