change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/tools/perf/util/cs-etm.h
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@@ -8,7 +8,9 @@
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 #define INCLUDE__UTIL_PERF_CS_ETM_H__
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 #include "util/event.h"
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-#include "util/session.h"
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+#include <linux/bits.h>
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+
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+struct perf_session;
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 /* Versionning header in case things need tro change in the future.  That way
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  * decoding of old snapshot is still possible.
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@@ -53,13 +55,117 @@
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 	CS_ETMV4_PRIV_MAX,
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 };
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+/*
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+ * ETMv3 exception encoding number:
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+ * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
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+ * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
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+ */
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+enum {
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+	CS_ETMV3_EXC_NONE = 0,
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+	CS_ETMV3_EXC_DEBUG_HALT = 1,
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+	CS_ETMV3_EXC_SMC = 2,
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+	CS_ETMV3_EXC_HYP = 3,
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+	CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
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+	CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
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+	CS_ETMV3_EXC_PE_RESET = 8,
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+	CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
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+	CS_ETMV3_EXC_SVC = 10,
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+	CS_ETMV3_EXC_PREFETCH_ABORT = 11,
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+	CS_ETMV3_EXC_DATA_FAULT = 12,
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+	CS_ETMV3_EXC_GENERIC = 13,
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+	CS_ETMV3_EXC_IRQ = 14,
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+	CS_ETMV3_EXC_FIQ = 15,
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+};
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+
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+/*
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+ * ETMv4 exception encoding number:
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+ * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
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+ * table 6-12 Possible values for the TYPE field in an Exception instruction
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+ * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
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+ */
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+enum {
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+	CS_ETMV4_EXC_RESET = 0,
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+	CS_ETMV4_EXC_DEBUG_HALT = 1,
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+	CS_ETMV4_EXC_CALL = 2,
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+	CS_ETMV4_EXC_TRAP = 3,
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+	CS_ETMV4_EXC_SYSTEM_ERROR = 4,
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+	CS_ETMV4_EXC_INST_DEBUG = 6,
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+	CS_ETMV4_EXC_DATA_DEBUG = 7,
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+	CS_ETMV4_EXC_ALIGNMENT = 10,
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+	CS_ETMV4_EXC_INST_FAULT = 11,
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+	CS_ETMV4_EXC_DATA_FAULT = 12,
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+	CS_ETMV4_EXC_IRQ = 14,
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+	CS_ETMV4_EXC_FIQ = 15,
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+	CS_ETMV4_EXC_END = 31,
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+};
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+
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+enum cs_etm_sample_type {
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+	CS_ETM_EMPTY,
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+	CS_ETM_RANGE,
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+	CS_ETM_DISCONTINUITY,
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+	CS_ETM_EXCEPTION,
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+	CS_ETM_EXCEPTION_RET,
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+};
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+
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+enum cs_etm_isa {
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+	CS_ETM_ISA_UNKNOWN,
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+	CS_ETM_ISA_A64,
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+	CS_ETM_ISA_A32,
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+	CS_ETM_ISA_T32,
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+};
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+
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+struct cs_etm_queue;
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+
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+struct cs_etm_packet {
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+	enum cs_etm_sample_type sample_type;
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+	enum cs_etm_isa isa;
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+	u64 start_addr;
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+	u64 end_addr;
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+	u32 instr_count;
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+	u32 last_instr_type;
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+	u32 last_instr_subtype;
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+	u32 flags;
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+	u32 exception_number;
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+	u8 last_instr_cond;
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+	u8 last_instr_taken_branch;
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+	u8 last_instr_size;
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+	u8 trace_chan_id;
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+	int cpu;
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+};
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+
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+#define CS_ETM_PACKET_MAX_BUFFER 1024
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+
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+/*
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+ * When working with per-thread scenarios the process under trace can
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+ * be scheduled on any CPU and as such, more than one traceID may be
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+ * associated with the same process.  Since a traceID of '0' is illegal
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+ * as per the CoreSight architecture, use that specific value to
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+ * identify the queue where all packets (with any traceID) are
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+ * aggregated.
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+ */
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+#define CS_ETM_PER_THREAD_TRACEID 0
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+
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+struct cs_etm_packet_queue {
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+	u32 packet_count;
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+	u32 head;
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+	u32 tail;
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+	u32 instr_count;
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+	u64 timestamp;
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+	u64 next_timestamp;
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+	struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
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+};
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+
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 #define KiB(x) ((x) * 1024)
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 #define MiB(x) ((x) * 1024 * 1024)
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+#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
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+
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+#define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
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+
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 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
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-static const u64 __perf_cs_etmv3_magic   = 0x3030303030303030ULL;
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-static const u64 __perf_cs_etmv4_magic   = 0x4040404040404040ULL;
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+#define __perf_cs_etmv3_magic 0x3030303030303030ULL
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+#define __perf_cs_etmv4_magic 0x4040404040404040ULL
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 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
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 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
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@@ -67,6 +173,13 @@
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 int cs_etm__process_auxtrace_info(union perf_event *event,
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 				  struct perf_session *session);
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 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
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+int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
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+			 pid_t tid, u8 trace_chan_id);
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+bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
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+void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
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+					      u8 trace_chan_id);
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+struct cs_etm_packet_queue
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+*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
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 #else
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 static inline int
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 cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
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@@ -80,6 +193,32 @@
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 {
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 	return -1;
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 }
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+
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+static inline int cs_etm__etmq_set_tid(
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+				struct cs_etm_queue *etmq __maybe_unused,
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+				pid_t tid __maybe_unused,
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+				u8 trace_chan_id __maybe_unused)
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+{
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+	return -1;
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+}
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+
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+static inline bool cs_etm__etmq_is_timeless(
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+				struct cs_etm_queue *etmq __maybe_unused)
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+{
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+	/* What else to return? */
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+	return true;
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+}
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+
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+static inline void cs_etm__etmq_set_traceid_queue_timestamp(
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+				struct cs_etm_queue *etmq __maybe_unused,
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+				u8 trace_chan_id __maybe_unused) {}
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+
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+static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(
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+				struct cs_etm_queue *etmq __maybe_unused,
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+				u8 trace_chan_id __maybe_unused)
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+{
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+	return NULL;
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+}
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 #endif
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 #endif