~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,6 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 and
6		- * only version 2 as published by the Free Software Foundation.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*
13	5	* lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
14	6	*/
..	..	@@ -31,7 +23,7 @@
31	23	int i2s_port;
32	24	};
33	25
34		-#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
	26	+#define LPASS_PLATFORM_BUFFER_SIZE (24 * 2 * 1024)
35	27	#define LPASS_PLATFORM_PERIODS 2
36	28
37	29	static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
..	..	@@ -58,17 +50,67 @@
58	50	.fifo_size = 0,
59	51	};
60	52
61		-static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
	53	+static int lpass_platform_alloc_dmactl_fields(struct device *dev,
	54	+ struct regmap *map)
	55	+{
	56	+ struct lpass_data *drvdata = dev_get_drvdata(dev);
	57	+ struct lpass_variant *v = drvdata->variant;
	58	+ struct lpaif_dmactl rd_dmactl, wr_dmactl;
	59	+ int rval;
	60	+
	61	+ drvdata->rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
	62	+ GFP_KERNEL);
	63	+ if (drvdata->rd_dmactl == NULL)
	64	+ return -ENOMEM;
	65	+
	66	+ drvdata->wr_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
	67	+ GFP_KERNEL);
	68	+ if (drvdata->wr_dmactl == NULL)
	69	+ return -ENOMEM;
	70	+
	71	+ rd_dmactl = drvdata->rd_dmactl;
	72	+ wr_dmactl = drvdata->wr_dmactl;
	73	+
	74	+ rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
	75	+ &v->rdma_intf, 6);
	76	+ if (rval)
	77	+ return rval;
	78	+
	79	+ return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
	80	+ &v->wrdma_intf, 6);
	81	+}
	82	+
	83	+static int lpass_platform_alloc_hdmidmactl_fields(struct device *dev,
	84	+ struct regmap *map)
	85	+{
	86	+ struct lpass_data *drvdata = dev_get_drvdata(dev);
	87	+ struct lpass_variant *v = drvdata->variant;
	88	+ struct lpaif_dmactl *rd_dmactl;
	89	+
	90	+ rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl), GFP_KERNEL);
	91	+ if (rd_dmactl == NULL)
	92	+ return -ENOMEM;
	93	+
	94	+ drvdata->hdmi_rd_dmactl = rd_dmactl;
	95	+
	96	+ return devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->bursten,
	97	+ &v->hdmi_rdma_bursten, 8);
	98	+}
	99	+
	100	+static int lpass_platform_pcmops_open(struct snd_soc_component *component,
	101	+ struct snd_pcm_substream *substream)
62	102	{
63	103	struct snd_pcm_runtime *runtime = substream->runtime;
64		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
65		- struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
66		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	104	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	105	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
67	106	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
68	107	struct lpass_variant *v = drvdata->variant;
69	108	int ret, dma_ch, dir = substream->stream;
70	109	struct lpass_pcm_data *data;
	110	+ struct regmap *map;
	111	+ unsigned int dai_id = cpu_dai->driver->id;
71	112
	113	+ component->id = dai_id;
72	114	data = kzalloc(sizeof(*data), GFP_KERNEL);
73	115	if (!data)
74	116	return -ENOMEM;
..	..	@@ -77,7 +119,7 @@
77	119	runtime->private_data = data;
78	120
79	121	if (v->alloc_dma_channel)
80		- dma_ch = v->alloc_dma_channel(drvdata, dir);
	122	+ dma_ch = v->alloc_dma_channel(drvdata, dir, dai_id);
81	123	else
82	124	dma_ch = 0;
83	125
..	..	@@ -86,18 +128,21 @@
86	128	return dma_ch;
87	129	}
88	130
89		- drvdata->substream[dma_ch] = substream;
90		-
91		- ret = regmap_write(drvdata->lpaif_map,
92		- LPAIF_DMACTL_REG(v, dma_ch, dir), 0);
	131	+ if (cpu_dai->driver->id == LPASS_DP_RX) {
	132	+ map = drvdata->hdmiif_map;
	133	+ drvdata->hdmi_substream[dma_ch] = substream;
	134	+ } else {
	135	+ map = drvdata->lpaif_map;
	136	+ drvdata->substream[dma_ch] = substream;
	137	+ }
	138	+ data->dma_ch = dma_ch;
	139	+ ret = regmap_write(map,
	140	+ LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0);
93	141	if (ret) {
94	142	dev_err(soc_runtime->dev,
95	143	"error writing to rdmactl reg: %d\n", ret);
96		- return ret;
	144	+ return ret;
97	145	}
98		-
99		- data->dma_ch = dma_ch;
100		-
101	146	snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
102	147
103	148	runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
..	..	@@ -116,29 +161,35 @@
116	161	return 0;
117	162	}
118	163
119		-static int lpass_platform_pcmops_close(struct snd_pcm_substream *substream)
	164	+static int lpass_platform_pcmops_close(struct snd_soc_component *component,
	165	+ struct snd_pcm_substream *substream)
120	166	{
121	167	struct snd_pcm_runtime *runtime = substream->runtime;
122		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
123		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	168	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	169	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
124	170	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
125	171	struct lpass_variant *v = drvdata->variant;
126	172	struct lpass_pcm_data *data;
	173	+ unsigned int dai_id = cpu_dai->driver->id;
127	174
128	175	data = runtime->private_data;
129		- drvdata->substream[data->dma_ch] = NULL;
	176	+ if (dai_id == LPASS_DP_RX)
	177	+ drvdata->hdmi_substream[data->dma_ch] = NULL;
	178	+ else
	179	+ drvdata->substream[data->dma_ch] = NULL;
130	180	if (v->free_dma_channel)
131		- v->free_dma_channel(drvdata, data->dma_ch);
	181	+ v->free_dma_channel(drvdata, data->dma_ch, dai_id);
132	182
133	183	kfree(data);
134	184	return 0;
135	185	}
136	186
137		-static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
138		- struct snd_pcm_hw_params *params)
	187	+static int lpass_platform_pcmops_hw_params(struct snd_soc_component *component,
	188	+ struct snd_pcm_substream *substream,
	189	+ struct snd_pcm_hw_params *params)
139	190	{
140		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
141		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	191	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	192	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
142	193	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
143	194	struct snd_pcm_runtime *rt = substream->runtime;
144	195	struct lpass_pcm_data *pcm_data = rt->private_data;
..	..	@@ -146,11 +197,23 @@
146	197	snd_pcm_format_t format = params_format(params);
147	198	unsigned int channels = params_channels(params);
148	199	unsigned int regval;
149		- int ch, dir = substream->stream;
	200	+ struct lpaif_dmactl *dmactl;
	201	+ int id, dir = substream->stream;
150	202	int bitwidth;
151	203	int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
	204	+ unsigned int dai_id = cpu_dai->driver->id;
152	205
153		- ch = pcm_data->dma_ch;
	206	+ if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
	207	+ id = pcm_data->dma_ch;
	208	+ if (dai_id == LPASS_DP_RX)
	209	+ dmactl = drvdata->hdmi_rd_dmactl;
	210	+ else
	211	+ dmactl = drvdata->rd_dmactl;
	212	+
	213	+ } else {
	214	+ dmactl = drvdata->wr_dmactl;
	215	+ id = pcm_data->dma_ch - v->wrdma_channel_start;
	216	+ }
154	217
155	218	bitwidth = snd_pcm_format_width(format);
156	219	if (bitwidth < 0) {
..	..	@@ -159,29 +222,75 @@
159	222	return bitwidth;
160	223	}
161	224
162		- regval = LPAIF_DMACTL_BURSTEN_INCR4 \|
163		- LPAIF_DMACTL_AUDINTF(dma_port) \|
164		- LPAIF_DMACTL_FIFOWM_8;
	225	+ ret = regmap_fields_write(dmactl->bursten, id, LPAIF_DMACTL_BURSTEN_INCR4);
	226	+ if (ret) {
	227	+ dev_err(soc_runtime->dev, "error updating bursten field: %d\n", ret);
	228	+ return ret;
	229	+ }
165	230
	231	+ ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
	232	+ if (ret) {
	233	+ dev_err(soc_runtime->dev, "error updating fifowm field: %d\n", ret);
	234	+ return ret;
	235	+ }
	236	+
	237	+ switch (dai_id) {
	238	+ case LPASS_DP_RX:
	239	+ ret = regmap_fields_write(dmactl->burst8, id,
	240	+ LPAIF_DMACTL_BURSTEN_INCR4);
	241	+ if (ret) {
	242	+ dev_err(soc_runtime->dev, "error updating burst8en field: %d\n", ret);
	243	+ return ret;
	244	+ }
	245	+ ret = regmap_fields_write(dmactl->burst16, id,
	246	+ LPAIF_DMACTL_BURSTEN_INCR4);
	247	+ if (ret) {
	248	+ dev_err(soc_runtime->dev, "error updating burst16en field: %d\n", ret);
	249	+ return ret;
	250	+ }
	251	+ ret = regmap_fields_write(dmactl->dynburst, id,
	252	+ LPAIF_DMACTL_BURSTEN_INCR4);
	253	+ if (ret) {
	254	+ dev_err(soc_runtime->dev, "error updating dynbursten field: %d\n", ret);
	255	+ return ret;
	256	+ }
	257	+ break;
	258	+ case MI2S_PRIMARY:
	259	+ case MI2S_SECONDARY:
	260	+ case MI2S_TERTIARY:
	261	+ case MI2S_QUATERNARY:
	262	+ case MI2S_QUINARY:
	263	+ ret = regmap_fields_write(dmactl->intf, id,
	264	+ LPAIF_DMACTL_AUDINTF(dma_port));
	265	+ if (ret) {
	266	+ dev_err(soc_runtime->dev, "error updating audio interface field: %d\n",
	267	+ ret);
	268	+ return ret;
	269	+ }
	270	+
	271	+ break;
	272	+ default:
	273	+ dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai_id);
	274	+ break;
	275	+ }
166	276	switch (bitwidth) {
167	277	case 16:
168	278	switch (channels) {
169	279	case 1:
170	280	case 2:
171		- regval \|= LPAIF_DMACTL_WPSCNT_ONE;
	281	+ regval = LPAIF_DMACTL_WPSCNT_ONE;
172	282	break;
173	283	case 4:
174		- regval \|= LPAIF_DMACTL_WPSCNT_TWO;
	284	+ regval = LPAIF_DMACTL_WPSCNT_TWO;
175	285	break;
176	286	case 6:
177		- regval \|= LPAIF_DMACTL_WPSCNT_THREE;
	287	+ regval = LPAIF_DMACTL_WPSCNT_THREE;
178	288	break;
179	289	case 8:
180		- regval \|= LPAIF_DMACTL_WPSCNT_FOUR;
	290	+ regval = LPAIF_DMACTL_WPSCNT_FOUR;
181	291	break;
182	292	default:
183		- dev_err(soc_runtime->dev,
184		- "invalid PCM config given: bw=%d, ch=%u\n",
	293	+ dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
185	294	bitwidth, channels);
186	295	return -EINVAL;
187	296	}
..	..	@@ -190,23 +299,30 @@
190	299	case 32:
191	300	switch (channels) {
192	301	case 1:
193		- regval \|= LPAIF_DMACTL_WPSCNT_ONE;
	302	+ regval = LPAIF_DMACTL_WPSCNT_ONE;
194	303	break;
195	304	case 2:
196		- regval \|= LPAIF_DMACTL_WPSCNT_TWO;
	305	+ regval = (dai_id == LPASS_DP_RX ?
	306	+ LPAIF_DMACTL_WPSCNT_ONE :
	307	+ LPAIF_DMACTL_WPSCNT_TWO);
197	308	break;
198	309	case 4:
199		- regval \|= LPAIF_DMACTL_WPSCNT_FOUR;
	310	+ regval = (dai_id == LPASS_DP_RX ?
	311	+ LPAIF_DMACTL_WPSCNT_TWO :
	312	+ LPAIF_DMACTL_WPSCNT_FOUR);
200	313	break;
201	314	case 6:
202		- regval \|= LPAIF_DMACTL_WPSCNT_SIX;
	315	+ regval = (dai_id == LPASS_DP_RX ?
	316	+ LPAIF_DMACTL_WPSCNT_THREE :
	317	+ LPAIF_DMACTL_WPSCNT_SIX);
203	318	break;
204	319	case 8:
205		- regval \|= LPAIF_DMACTL_WPSCNT_EIGHT;
	320	+ regval = (dai_id == LPASS_DP_RX ?
	321	+ LPAIF_DMACTL_WPSCNT_FOUR :
	322	+ LPAIF_DMACTL_WPSCNT_EIGHT);
206	323	break;
207	324	default:
208		- dev_err(soc_runtime->dev,
209		- "invalid PCM config given: bw=%d, ch=%u\n",
	325	+ dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
210	326	bitwidth, channels);
211	327	return -EINVAL;
212	328	}
..	..	@@ -217,10 +333,9 @@
217	333	return -EINVAL;
218	334	}
219	335
220		- ret = regmap_write(drvdata->lpaif_map,
221		- LPAIF_DMACTL_REG(v, ch, dir), regval);
	336	+ ret = regmap_fields_write(dmactl->wpscnt, id, regval);
222	337	if (ret) {
223		- dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
	338	+ dev_err(soc_runtime->dev, "error writing to dmactl reg: %d\n",
224	339	ret);
225	340	return ret;
226	341	}
..	..	@@ -228,19 +343,27 @@
228	343	return 0;
229	344	}
230	345
231		-static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
	346	+static int lpass_platform_pcmops_hw_free(struct snd_soc_component *component,
	347	+ struct snd_pcm_substream *substream)
232	348	{
233		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
234		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	349	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	350	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
235	351	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
236	352	struct snd_pcm_runtime *rt = substream->runtime;
237	353	struct lpass_pcm_data *pcm_data = rt->private_data;
238	354	struct lpass_variant *v = drvdata->variant;
239	355	unsigned int reg;
240	356	int ret;
	357	+ struct regmap *map;
	358	+ unsigned int dai_id = cpu_dai->driver->id;
241	359
242		- reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream);
243		- ret = regmap_write(drvdata->lpaif_map, reg, 0);
	360	+ if (dai_id == LPASS_DP_RX)
	361	+ map = drvdata->hdmiif_map;
	362	+ else
	363	+ map = drvdata->lpaif_map;
	364	+
	365	+ reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream, dai_id);
	366	+ ret = regmap_write(map, reg, 0);
244	367	if (ret)
245	368	dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
246	369	ret);
..	..	@@ -248,30 +371,48 @@
248	371	return ret;
249	372	}
250	373
251		-static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
	374	+static int lpass_platform_pcmops_prepare(struct snd_soc_component *component,
	375	+ struct snd_pcm_substream *substream)
252	376	{
253	377	struct snd_pcm_runtime *runtime = substream->runtime;
254		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
255		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	378	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	379	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
256	380	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
257	381	struct snd_pcm_runtime *rt = substream->runtime;
258	382	struct lpass_pcm_data *pcm_data = rt->private_data;
259	383	struct lpass_variant *v = drvdata->variant;
260		- int ret, ch, dir = substream->stream;
	384	+ struct lpaif_dmactl *dmactl;
	385	+ struct regmap *map;
	386	+ int ret, id, ch, dir = substream->stream;
	387	+ unsigned int dai_id = cpu_dai->driver->id;
	388	+
261	389
262	390	ch = pcm_data->dma_ch;
	391	+ if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
	392	+ if (dai_id == LPASS_DP_RX) {
	393	+ dmactl = drvdata->hdmi_rd_dmactl;
	394	+ map = drvdata->hdmiif_map;
	395	+ } else {
	396	+ dmactl = drvdata->rd_dmactl;
	397	+ map = drvdata->lpaif_map;
	398	+ }
263	399
264		- ret = regmap_write(drvdata->lpaif_map,
265		- LPAIF_DMABASE_REG(v, ch, dir),
266		- runtime->dma_addr);
	400	+ id = pcm_data->dma_ch;
	401	+ } else {
	402	+ dmactl = drvdata->wr_dmactl;
	403	+ id = pcm_data->dma_ch - v->wrdma_channel_start;
	404	+ map = drvdata->lpaif_map;
	405	+ }
	406	+
	407	+ ret = regmap_write(map, LPAIF_DMABASE_REG(v, ch, dir, dai_id),
	408	+ runtime->dma_addr);
267	409	if (ret) {
268	410	dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
269	411	ret);
270	412	return ret;
271	413	}
272	414
273		- ret = regmap_write(drvdata->lpaif_map,
274		- LPAIF_DMABUFF_REG(v, ch, dir),
	415	+ ret = regmap_write(map, LPAIF_DMABUFF_REG(v, ch, dir, dai_id),
275	416	(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
276	417	if (ret) {
277	418	dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
..	..	@@ -279,8 +420,7 @@
279	420	return ret;
280	421	}
281	422
282		- ret = regmap_write(drvdata->lpaif_map,
283		- LPAIF_DMAPER_REG(v, ch, dir),
	423	+ ret = regmap_write(map, LPAIF_DMAPER_REG(v, ch, dir, dai_id),
284	424	(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
285	425	if (ret) {
286	426	dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
..	..	@@ -288,9 +428,7 @@
288	428	return ret;
289	429	}
290	430
291		- ret = regmap_update_bits(drvdata->lpaif_map,
292		- LPAIF_DMACTL_REG(v, ch, dir),
293		- LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
	431	+ ret = regmap_fields_write(dmactl->enable, id, LPAIF_DMACTL_ENABLE_ON);
294	432	if (ret) {
295	433	dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
296	434	ret);
..	..	@@ -300,69 +438,146 @@
300	438	return 0;
301	439	}
302	440
303		-static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
304		- int cmd)
	441	+static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,
	442	+ struct snd_pcm_substream *substream,
	443	+ int cmd)
305	444	{
306		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
307		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	445	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	446	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
308	447	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
309	448	struct snd_pcm_runtime *rt = substream->runtime;
310	449	struct lpass_pcm_data *pcm_data = rt->private_data;
311	450	struct lpass_variant *v = drvdata->variant;
312		- int ret, ch, dir = substream->stream;
	451	+ struct lpaif_dmactl *dmactl;
	452	+ struct regmap *map;
	453	+ int ret, ch, id;
	454	+ int dir = substream->stream;
	455	+ unsigned int reg_irqclr = 0, val_irqclr = 0;
	456	+ unsigned int reg_irqen = 0, val_irqen = 0, val_mask = 0;
	457	+ unsigned int dai_id = cpu_dai->driver->id;
313	458
314	459	ch = pcm_data->dma_ch;
	460	+ if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
	461	+ id = pcm_data->dma_ch;
	462	+ if (dai_id == LPASS_DP_RX) {
	463	+ dmactl = drvdata->hdmi_rd_dmactl;
	464	+ map = drvdata->hdmiif_map;
	465	+ } else {
	466	+ dmactl = drvdata->rd_dmactl;
	467	+ map = drvdata->lpaif_map;
	468	+ }
	469	+ } else {
	470	+ dmactl = drvdata->wr_dmactl;
	471	+ id = pcm_data->dma_ch - v->wrdma_channel_start;
	472	+ map = drvdata->lpaif_map;
	473	+ }
315	474
316	475	switch (cmd) {
317	476	case SNDRV_PCM_TRIGGER_START:
318	477	case SNDRV_PCM_TRIGGER_RESUME:
319	478	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
320		- /* clear status before enabling interrupts */
321		- ret = regmap_write(drvdata->lpaif_map,
322		- LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
323		- LPAIF_IRQ_ALL(ch));
324		- if (ret) {
325		- dev_err(soc_runtime->dev,
326		- "error writing to irqclear reg: %d\n", ret);
327		- return ret;
328		- }
329		-
330		- ret = regmap_update_bits(drvdata->lpaif_map,
331		- LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
332		- LPAIF_IRQ_ALL(ch),
333		- LPAIF_IRQ_ALL(ch));
334		- if (ret) {
335		- dev_err(soc_runtime->dev,
336		- "error writing to irqen reg: %d\n", ret);
337		- return ret;
338		- }
339		-
340		- ret = regmap_update_bits(drvdata->lpaif_map,
341		- LPAIF_DMACTL_REG(v, ch, dir),
342		- LPAIF_DMACTL_ENABLE_MASK,
343		- LPAIF_DMACTL_ENABLE_ON);
	479	+ ret = regmap_fields_write(dmactl->enable, id,
	480	+ LPAIF_DMACTL_ENABLE_ON);
344	481	if (ret) {
345	482	dev_err(soc_runtime->dev,
346	483	"error writing to rdmactl reg: %d\n", ret);
	484	+ return ret;
	485	+ }
	486	+ switch (dai_id) {
	487	+ case LPASS_DP_RX:
	488	+ ret = regmap_fields_write(dmactl->dyncclk, id,
	489	+ LPAIF_DMACTL_DYNCLK_ON);
	490	+ if (ret) {
	491	+ dev_err(soc_runtime->dev,
	492	+ "error writing to rdmactl reg: %d\n", ret);
	493	+ return ret;
	494	+ }
	495	+ reg_irqclr = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
	496	+ val_irqclr = (LPAIF_IRQ_ALL(ch) \|
	497	+ LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) \|
	498	+ LPAIF_IRQ_HDMI_METADONE \|
	499	+ LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
	500	+
	501	+ reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
	502	+ val_mask = (LPAIF_IRQ_ALL(ch) \|
	503	+ LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) \|
	504	+ LPAIF_IRQ_HDMI_METADONE \|
	505	+ LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
	506	+ val_irqen = (LPAIF_IRQ_ALL(ch) \|
	507	+ LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) \|
	508	+ LPAIF_IRQ_HDMI_METADONE \|
	509	+ LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
	510	+ break;
	511	+ case MI2S_PRIMARY:
	512	+ case MI2S_SECONDARY:
	513	+ case MI2S_TERTIARY:
	514	+ case MI2S_QUATERNARY:
	515	+ case MI2S_QUINARY:
	516	+ reg_irqclr = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
	517	+ val_irqclr = LPAIF_IRQ_ALL(ch);
	518	+
	519	+
	520	+ reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
	521	+ val_mask = LPAIF_IRQ_ALL(ch);
	522	+ val_irqen = LPAIF_IRQ_ALL(ch);
	523	+ break;
	524	+ default:
	525	+ dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
	526	+ return -EINVAL;
	527	+ }
	528	+
	529	+ ret = regmap_write(map, reg_irqclr, val_irqclr);
	530	+ if (ret) {
	531	+ dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret);
	532	+ return ret;
	533	+ }
	534	+ ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
	535	+ if (ret) {
	536	+ dev_err(soc_runtime->dev, "error writing to irqen reg: %d\n", ret);
347	537	return ret;
348	538	}
349	539	break;
350	540	case SNDRV_PCM_TRIGGER_STOP:
351	541	case SNDRV_PCM_TRIGGER_SUSPEND:
352	542	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
353		- ret = regmap_update_bits(drvdata->lpaif_map,
354		- LPAIF_DMACTL_REG(v, ch, dir),
355		- LPAIF_DMACTL_ENABLE_MASK,
356		- LPAIF_DMACTL_ENABLE_OFF);
	543	+ ret = regmap_fields_write(dmactl->enable, id,
	544	+ LPAIF_DMACTL_ENABLE_OFF);
357	545	if (ret) {
358	546	dev_err(soc_runtime->dev,
359	547	"error writing to rdmactl reg: %d\n", ret);
360	548	return ret;
361	549	}
	550	+ switch (dai_id) {
	551	+ case LPASS_DP_RX:
	552	+ ret = regmap_fields_write(dmactl->dyncclk, id,
	553	+ LPAIF_DMACTL_DYNCLK_OFF);
	554	+ if (ret) {
	555	+ dev_err(soc_runtime->dev,
	556	+ "error writing to rdmactl reg: %d\n", ret);
	557	+ return ret;
	558	+ }
	559	+ reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
	560	+ val_mask = (LPAIF_IRQ_ALL(ch) \|
	561	+ LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) \|
	562	+ LPAIF_IRQ_HDMI_METADONE \|
	563	+ LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
	564	+ val_irqen = 0;
	565	+ break;
	566	+ case MI2S_PRIMARY:
	567	+ case MI2S_SECONDARY:
	568	+ case MI2S_TERTIARY:
	569	+ case MI2S_QUATERNARY:
	570	+ case MI2S_QUINARY:
	571	+ reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
	572	+ val_mask = LPAIF_IRQ_ALL(ch);
	573	+ val_irqen = 0;
	574	+ break;
	575	+ default:
	576	+ dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
	577	+ return -EINVAL;
	578	+ }
362	579
363		- ret = regmap_update_bits(drvdata->lpaif_map,
364		- LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
365		- LPAIF_IRQ_ALL(ch), 0);
	580	+ ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
366	581	if (ret) {
367	582	dev_err(soc_runtime->dev,
368	583	"error writing to irqen reg: %d\n", ret);
..	..	@@ -375,29 +590,37 @@
375	590	}
376	591
377	592	static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
	593	+ struct snd_soc_component *component,
378	594	struct snd_pcm_substream *substream)
379	595	{
380		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
381		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
	596	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	597	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
382	598	struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
383	599	struct snd_pcm_runtime *rt = substream->runtime;
384	600	struct lpass_pcm_data *pcm_data = rt->private_data;
385	601	struct lpass_variant *v = drvdata->variant;
386	602	unsigned int base_addr, curr_addr;
387	603	int ret, ch, dir = substream->stream;
	604	+ struct regmap *map;
	605	+ unsigned int dai_id = cpu_dai->driver->id;
	606	+
	607	+ if (dai_id == LPASS_DP_RX)
	608	+ map = drvdata->hdmiif_map;
	609	+ else
	610	+ map = drvdata->lpaif_map;
388	611
389	612	ch = pcm_data->dma_ch;
390	613
391		- ret = regmap_read(drvdata->lpaif_map,
392		- LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
	614	+ ret = regmap_read(map,
	615	+ LPAIF_DMABASE_REG(v, ch, dir, dai_id), &base_addr);
393	616	if (ret) {
394	617	dev_err(soc_runtime->dev,
395	618	"error reading from rdmabase reg: %d\n", ret);
396	619	return ret;
397	620	}
398	621
399		- ret = regmap_read(drvdata->lpaif_map,
400		- LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
	622	+ ret = regmap_read(map,
	623	+ LPAIF_DMACURR_REG(v, ch, dir, dai_id), &curr_addr);
401	624	if (ret) {
402	625	dev_err(soc_runtime->dev,
403	626	"error reading from rdmacurr reg: %d\n", ret);
..	..	@@ -407,42 +630,54 @@
407	630	return bytes_to_frames(substream->runtime, curr_addr - base_addr);
408	631	}
409	632
410		-static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
411		- struct vm_area_struct *vma)
	633	+static int lpass_platform_pcmops_mmap(struct snd_soc_component *component,
	634	+ struct snd_pcm_substream *substream,
	635	+ struct vm_area_struct *vma)
412	636	{
413	637	struct snd_pcm_runtime *runtime = substream->runtime;
414	638
415		- return dma_mmap_coherent(substream->pcm->card->dev, vma,
416		- runtime->dma_area, runtime->dma_addr,
417		- runtime->dma_bytes);
	639	+ return dma_mmap_coherent(component->dev, vma, runtime->dma_area,
	640	+ runtime->dma_addr, runtime->dma_bytes);
418	641	}
419		-
420		-static const struct snd_pcm_ops lpass_platform_pcm_ops = {
421		- .open = lpass_platform_pcmops_open,
422		- .close = lpass_platform_pcmops_close,
423		- .ioctl = snd_pcm_lib_ioctl,
424		- .hw_params = lpass_platform_pcmops_hw_params,
425		- .hw_free = lpass_platform_pcmops_hw_free,
426		- .prepare = lpass_platform_pcmops_prepare,
427		- .trigger = lpass_platform_pcmops_trigger,
428		- .pointer = lpass_platform_pcmops_pointer,
429		- .mmap = lpass_platform_pcmops_mmap,
430		-};
431	642
432	643	static irqreturn_t lpass_dma_interrupt_handler(
433	644	struct snd_pcm_substream *substream,
434	645	struct lpass_data *drvdata,
435	646	int chan, u32 interrupts)
436	647	{
437		- struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
	648	+ struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
	649	+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
438	650	struct lpass_variant *v = drvdata->variant;
439	651	irqreturn_t ret = IRQ_NONE;
440	652	int rv;
	653	+ unsigned int reg = 0, val = 0;
	654	+ struct regmap *map;
	655	+ unsigned int dai_id = cpu_dai->driver->id;
441	656
	657	+ switch (dai_id) {
	658	+ case LPASS_DP_RX:
	659	+ map = drvdata->hdmiif_map;
	660	+ reg = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
	661	+ val = (LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) \|
	662	+ LPAIF_IRQ_HDMI_METADONE \|
	663	+ LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan));
	664	+ break;
	665	+ case MI2S_PRIMARY:
	666	+ case MI2S_SECONDARY:
	667	+ case MI2S_TERTIARY:
	668	+ case MI2S_QUATERNARY:
	669	+ case MI2S_QUINARY:
	670	+ map = drvdata->lpaif_map;
	671	+ reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
	672	+ val = 0;
	673	+ break;
	674	+ default:
	675	+ dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
	676	+ return -EINVAL;
	677	+ }
442	678	if (interrupts & LPAIF_IRQ_PER(chan)) {
443		- rv = regmap_write(drvdata->lpaif_map,
444		- LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
445		- LPAIF_IRQ_PER(chan));
	679	+
	680	+ rv = regmap_write(map, reg, LPAIF_IRQ_PER(chan) \| val);
446	681	if (rv) {
447	682	dev_err(soc_runtime->dev,
448	683	"error writing to irqclear reg: %d\n", rv);
..	..	@@ -453,9 +688,7 @@
453	688	}
454	689
455	690	if (interrupts & LPAIF_IRQ_XRUN(chan)) {
456		- rv = regmap_write(drvdata->lpaif_map,
457		- LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
458		- LPAIF_IRQ_XRUN(chan));
	691	+ rv = regmap_write(map, reg, LPAIF_IRQ_XRUN(chan) \| val);
459	692	if (rv) {
460	693	dev_err(soc_runtime->dev,
461	694	"error writing to irqclear reg: %d\n", rv);
..	..	@@ -467,9 +700,7 @@
467	700	}
468	701
469	702	if (interrupts & LPAIF_IRQ_ERR(chan)) {
470		- rv = regmap_write(drvdata->lpaif_map,
471		- LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
472		- LPAIF_IRQ_ERR(chan));
	703	+ rv = regmap_write(map, reg, LPAIF_IRQ_ERR(chan) \| val);
473	704	if (rv) {
474	705	dev_err(soc_runtime->dev,
475	706	"error writing to irqclear reg: %d\n", rv);
..	..	@@ -477,6 +708,16 @@
477	708	}
478	709	dev_err(soc_runtime->dev, "bus access error\n");
479	710	snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
	711	+ ret = IRQ_HANDLED;
	712	+ }
	713	+
	714	+ if (interrupts & val) {
	715	+ rv = regmap_write(map, reg, val);
	716	+ if (rv) {
	717	+ dev_err(soc_runtime->dev,
	718	+ "error writing to irqclear reg: %d\n", rv);
	719	+ return IRQ_NONE;
	720	+ }
480	721	ret = IRQ_HANDLED;
481	722	}
482	723
..	..	@@ -511,11 +752,42 @@
511	752	return IRQ_HANDLED;
512	753	}
513	754
514		-static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
	755	+static irqreturn_t lpass_platform_hdmiif_irq(int irq, void *data)
	756	+{
	757	+ struct lpass_data *drvdata = data;
	758	+ struct lpass_variant *v = drvdata->variant;
	759	+ unsigned int irqs;
	760	+ int rv, chan;
	761	+
	762	+ rv = regmap_read(drvdata->hdmiif_map,
	763	+ LPASS_HDMITX_APP_IRQSTAT_REG(v), &irqs);
	764	+ if (rv) {
	765	+ pr_err("error reading from irqstat reg: %d\n", rv);
	766	+ return IRQ_NONE;
	767	+ }
	768	+
	769	+ /* Handle per channel interrupts */
	770	+ for (chan = 0; chan < LPASS_MAX_HDMI_DMA_CHANNELS; chan++) {
	771	+ if (irqs & (LPAIF_IRQ_ALL(chan) \| LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) \|
	772	+ LPAIF_IRQ_HDMI_METADONE \|
	773	+ LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan))
	774	+ && drvdata->hdmi_substream[chan]) {
	775	+ rv = lpass_dma_interrupt_handler(
	776	+ drvdata->hdmi_substream[chan],
	777	+ drvdata, chan, irqs);
	778	+ if (rv != IRQ_HANDLED)
	779	+ return rv;
	780	+ }
	781	+ }
	782	+
	783	+ return IRQ_HANDLED;
	784	+}
	785	+
	786	+static int lpass_platform_pcm_new(struct snd_soc_component *component,
	787	+ struct snd_soc_pcm_runtime *soc_runtime)
515	788	{
516	789	struct snd_pcm *pcm = soc_runtime->pcm;
517	790	struct snd_pcm_substream psubstream, csubstream;
518		- struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
519	791	int ret = -EINVAL;
520	792	size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
521	793
..	..	@@ -547,12 +819,13 @@
547	819	return 0;
548	820	}
549	821
550		-static void lpass_platform_pcm_free(struct snd_pcm *pcm)
	822	+static void lpass_platform_pcm_free(struct snd_soc_component *component,
	823	+ struct snd_pcm *pcm)
551	824	{
552	825	struct snd_pcm_substream *substream;
553	826	int i;
554	827
555		- for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
	828	+ for_each_pcm_streams(i) {
556	829	substream = pcm->streams[i].substream;
557	830	if (substream) {
558	831	snd_dma_free_pages(&substream->dma_buffer);
..	..	@@ -564,9 +837,17 @@
564	837
565	838	static const struct snd_soc_component_driver lpass_component_driver = {
566	839	.name = DRV_NAME,
567		- .pcm_new = lpass_platform_pcm_new,
568		- .pcm_free = lpass_platform_pcm_free,
569		- .ops = &lpass_platform_pcm_ops,
	840	+ .open = lpass_platform_pcmops_open,
	841	+ .close = lpass_platform_pcmops_close,
	842	+ .hw_params = lpass_platform_pcmops_hw_params,
	843	+ .hw_free = lpass_platform_pcmops_hw_free,
	844	+ .prepare = lpass_platform_pcmops_prepare,
	845	+ .trigger = lpass_platform_pcmops_trigger,
	846	+ .pointer = lpass_platform_pcmops_pointer,
	847	+ .mmap = lpass_platform_pcmops_mmap,
	848	+ .pcm_construct = lpass_platform_pcm_new,
	849	+ .pcm_destruct = lpass_platform_pcm_free,
	850	+
570	851	};
571	852
572	853	int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
..	..	@@ -576,11 +857,8 @@
576	857	int ret;
577	858
578	859	drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
579		- if (drvdata->lpaif_irq < 0) {
580		- dev_err(&pdev->dev, "error getting irq handle: %d\n",
581		- drvdata->lpaif_irq);
	860	+ if (drvdata->lpaif_irq < 0)
582	861	return -ENODEV;
583		- }
584	862
585	863	/* ensure audio hardware is disabled */
586	864	ret = regmap_write(drvdata->lpaif_map,
..	..	@@ -598,7 +876,40 @@
598	876	return ret;
599	877	}
600	878
	879	+ ret = lpass_platform_alloc_dmactl_fields(&pdev->dev,
	880	+ drvdata->lpaif_map);
	881	+ if (ret) {
	882	+ dev_err(&pdev->dev,
	883	+ "error initializing dmactl fields: %d\n", ret);
	884	+ return ret;
	885	+ }
601	886
	887	+ if (drvdata->hdmi_port_enable) {
	888	+ drvdata->hdmiif_irq = platform_get_irq_byname(pdev, "lpass-irq-hdmi");
	889	+ if (drvdata->hdmiif_irq < 0)
	890	+ return -ENODEV;
	891	+
	892	+ ret = devm_request_irq(&pdev->dev, drvdata->hdmiif_irq,
	893	+ lpass_platform_hdmiif_irq, 0, "lpass-irq-hdmi", drvdata);
	894	+ if (ret) {
	895	+ dev_err(&pdev->dev, "irq hdmi request failed: %d\n", ret);
	896	+ return ret;
	897	+ }
	898	+ ret = regmap_write(drvdata->hdmiif_map,
	899	+ LPASS_HDMITX_APP_IRQEN_REG(v), 0);
	900	+ if (ret) {
	901	+ dev_err(&pdev->dev, "error writing to hdmi irqen reg: %d\n", ret);
	902	+ return ret;
	903	+ }
	904	+
	905	+ ret = lpass_platform_alloc_hdmidmactl_fields(&pdev->dev,
	906	+ drvdata->hdmiif_map);
	907	+ if (ret) {
	908	+ dev_err(&pdev->dev,
	909	+ "error initializing hdmidmactl fields: %d\n", ret);
	910	+ return ret;
	911	+ }
	912	+ }
602	913	return devm_snd_soc_register_component(&pdev->dev,
603	914	&lpass_component_driver, NULL, 0);
604	915	}