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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2015 Linaro Ltd. |
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| 3 | 4 | * Author: Shannon Zhao <shannon.zhao@linaro.org> |
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| 4 | | - * |
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| 5 | | - * This program is free software; you can redistribute it and/or modify |
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| 6 | | - * it under the terms of the GNU General Public License version 2 as |
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| 7 | | - * published by the Free Software Foundation. |
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| 8 | | - * |
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| 9 | | - * This program is distributed in the hope that it will be useful, |
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| 10 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 12 | | - * GNU General Public License for more details. |
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| 13 | | - * |
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| 14 | | - * You should have received a copy of the GNU General Public License |
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| 15 | | - * along with this program. If not, see <http://www.gnu.org/licenses/>. |
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| 16 | 5 | */ |
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| 17 | 6 | |
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| 18 | 7 | #ifndef __ASM_ARM_KVM_PMU_H |
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| .. | .. |
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| 22 | 11 | #include <asm/perf_event.h> |
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| 23 | 12 | |
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| 24 | 13 | #define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1) |
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| 14 | +#define ARMV8_PMU_MAX_COUNTER_PAIRS ((ARMV8_PMU_MAX_COUNTERS + 1) >> 1) |
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| 25 | 15 | |
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| 26 | | -#ifdef CONFIG_KVM_ARM_PMU |
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| 16 | +DECLARE_STATIC_KEY_FALSE(kvm_arm_pmu_available); |
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| 17 | + |
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| 18 | +static __always_inline bool kvm_arm_support_pmu_v3(void) |
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| 19 | +{ |
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| 20 | + return static_branch_likely(&kvm_arm_pmu_available); |
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| 21 | +} |
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| 22 | + |
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| 23 | +#ifdef CONFIG_HW_PERF_EVENTS |
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| 27 | 24 | |
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| 28 | 25 | struct kvm_pmc { |
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| 29 | 26 | u8 idx; /* index into the pmu->pmc array */ |
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| 30 | 27 | struct perf_event *perf_event; |
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| 31 | | - u64 bitmask; |
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| 32 | 28 | }; |
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| 33 | 29 | |
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| 34 | 30 | struct kvm_pmu { |
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| 35 | 31 | int irq_num; |
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| 36 | 32 | struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS]; |
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| 37 | | - bool ready; |
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| 33 | + DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS); |
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| 38 | 34 | bool created; |
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| 39 | 35 | bool irq_level; |
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| 36 | + struct irq_work overflow_work; |
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| 40 | 37 | }; |
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| 41 | 38 | |
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| 42 | | -#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready) |
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| 43 | 39 | #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS) |
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| 44 | 40 | u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx); |
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| 45 | 41 | void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val); |
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| 46 | 42 | u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu); |
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| 43 | +u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1); |
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| 44 | +void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu); |
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| 47 | 45 | void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu); |
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| 48 | 46 | void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu); |
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| 49 | | -void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val); |
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| 50 | | -void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val); |
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| 47 | +void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val); |
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| 48 | +void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val); |
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| 51 | 49 | void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu); |
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| 52 | 50 | void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu); |
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| 53 | 51 | bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu); |
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| .. | .. |
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| 56 | 54 | void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val); |
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| 57 | 55 | void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, |
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| 58 | 56 | u64 select_idx); |
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| 59 | | -bool kvm_arm_support_pmu_v3(void); |
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| 60 | 57 | int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, |
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| 61 | 58 | struct kvm_device_attr *attr); |
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| 62 | 59 | int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, |
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| .. | .. |
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| 68 | 65 | struct kvm_pmu { |
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| 69 | 66 | }; |
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| 70 | 67 | |
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| 71 | | -#define kvm_arm_pmu_v3_ready(v) (false) |
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| 72 | 68 | #define kvm_arm_pmu_irq_initialized(v) (false) |
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| 73 | 69 | static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, |
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| 74 | 70 | u64 select_idx) |
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| .. | .. |
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| 81 | 77 | { |
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| 82 | 78 | return 0; |
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| 83 | 79 | } |
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| 80 | +static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {} |
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| 84 | 81 | static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {} |
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| 85 | 82 | static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {} |
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| 86 | | -static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {} |
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| 87 | | -static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {} |
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| 83 | +static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {} |
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| 84 | +static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {} |
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| 88 | 85 | static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {} |
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| 89 | 86 | static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {} |
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| 90 | 87 | static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu) |
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| .. | .. |
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| 96 | 93 | static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {} |
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| 97 | 94 | static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, |
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| 98 | 95 | u64 data, u64 select_idx) {} |
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| 99 | | -static inline bool kvm_arm_support_pmu_v3(void) { return false; } |
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| 100 | 96 | static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, |
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| 101 | 97 | struct kvm_device_attr *attr) |
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| 102 | 98 | { |
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| .. | .. |
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| 116 | 112 | { |
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| 117 | 113 | return 0; |
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| 118 | 114 | } |
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| 115 | +static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) |
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| 116 | +{ |
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| 117 | + return 0; |
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| 118 | +} |
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| 119 | 119 | #endif |
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| 120 | 120 | |
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| 121 | 121 | #endif |
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