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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright 2017 Texas Instruments, Inc. |
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| 3 | | - * |
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| 4 | | - * This software is licensed under the terms of the GNU General Public |
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| 5 | | - * License version 2, as published by the Free Software Foundation, and |
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| 6 | | - * may be copied, distributed, and modified under those terms. |
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| 7 | | - * |
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| 8 | | - * This program is distributed in the hope that it will be useful, |
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| 9 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 10 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 11 | | - * GNU General Public License for more details. |
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| 12 | 4 | */ |
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| 13 | 5 | #ifndef __DT_BINDINGS_CLK_OMAP5_H |
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| 14 | 6 | #define __DT_BINDINGS_CLK_OMAP5_H |
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| .. | .. |
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| 24 | 16 | |
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| 25 | 17 | /* abe clocks */ |
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| 26 | 18 | #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
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| 19 | +#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
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| 27 | 20 | #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
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| 28 | 21 | #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) |
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| 29 | 22 | #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) |
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| .. | .. |
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| 94 | 87 | #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) |
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| 95 | 88 | #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) |
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| 96 | 89 | |
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| 90 | +/* l4_secure clocks */ |
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| 91 | +#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 |
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| 92 | +#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) |
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| 93 | +#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) |
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| 94 | +#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) |
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| 95 | +#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) |
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| 96 | +#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) |
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| 97 | +#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) |
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| 98 | +#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) |
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| 99 | +#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) |
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| 100 | + |
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| 101 | +/* iva clocks */ |
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| 102 | +#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
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| 103 | +#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
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| 104 | + |
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| 97 | 105 | /* dss clocks */ |
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| 98 | 106 | #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
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| 99 | 107 | |
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| 108 | +/* gpu clocks */ |
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| 109 | +#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) |
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| 110 | + |
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| 100 | 111 | /* l3init clocks */ |
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| 101 | 112 | #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) |
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| 102 | 113 | #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) |
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