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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/include/asm-generic/io.h
....@@ -1,12 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /* Generic I/O port emulation.
23  *
34  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
45  * Written by David Howells (dhowells@redhat.com)
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public Licence
8
- * as published by the Free Software Foundation; either version
9
- * 2 of the Licence, or (at your option) any later version.
106  */
117 #ifndef __ASM_GENERIC_IO_H
128 #define __ASM_GENERIC_IO_H
....@@ -19,11 +15,8 @@
1915 #include <asm-generic/iomap.h>
2016 #endif
2117 
18
+#include <asm/mmiowb.h>
2219 #include <asm-generic/pci_iomap.h>
23
-
24
-#ifndef mmiowb
25
-#define mmiowb() do {} while (0)
26
-#endif
2720 
2821 #ifndef __io_br
2922 #define __io_br()      barrier()
....@@ -32,9 +25,9 @@
3225 /* prevent prefetching of coherent DMA data ahead of a dma-complete */
3326 #ifndef __io_ar
3427 #ifdef rmb
35
-#define __io_ar()      rmb()
28
+#define __io_ar(v)      rmb()
3629 #else
37
-#define __io_ar()      barrier()
30
+#define __io_ar(v)      barrier()
3831 #endif
3932 #endif
4033 
....@@ -49,7 +42,7 @@
4942 
5043 /* serialize device access against a spin_unlock, usually handled there. */
5144 #ifndef __io_aw
52
-#define __io_aw()      barrier()
45
+#define __io_aw()      mmiowb_set_pending()
5346 #endif
5447 
5548 #ifndef __io_pbw
....@@ -65,7 +58,7 @@
6558 #endif
6659 
6760 #ifndef __io_par
68
-#define __io_par()     __io_ar()
61
+#define __io_par(v)     __io_ar(v)
6962 #endif
7063 
7164 
....@@ -158,7 +151,7 @@
158151 
159152 	__io_br();
160153 	val = __raw_readb(addr);
161
-	__io_ar();
154
+	__io_ar(val);
162155 	return val;
163156 }
164157 #endif
....@@ -170,8 +163,8 @@
170163 	u16 val;
171164 
172165 	__io_br();
173
-	val = __le16_to_cpu(__raw_readw(addr));
174
-	__io_ar();
166
+	val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
167
+	__io_ar(val);
175168 	return val;
176169 }
177170 #endif
....@@ -183,8 +176,8 @@
183176 	u32 val;
184177 
185178 	__io_br();
186
-	val = __le32_to_cpu(__raw_readl(addr));
187
-	__io_ar();
179
+	val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
180
+	__io_ar(val);
188181 	return val;
189182 }
190183 #endif
....@@ -197,8 +190,8 @@
197190 	u64 val;
198191 
199192 	__io_br();
200
-	val = __le64_to_cpu(__raw_readq(addr));
201
-	__io_ar();
193
+	val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
194
+	__io_ar(val);
202195 	return val;
203196 }
204197 #endif
....@@ -219,7 +212,7 @@
219212 static inline void writew(u16 value, volatile void __iomem *addr)
220213 {
221214 	__io_bw();
222
-	__raw_writew(cpu_to_le16(value), addr);
215
+	__raw_writew((u16 __force)cpu_to_le16(value), addr);
223216 	__io_aw();
224217 }
225218 #endif
....@@ -229,7 +222,7 @@
229222 static inline void writel(u32 value, volatile void __iomem *addr)
230223 {
231224 	__io_bw();
232
-	__raw_writel(__cpu_to_le32(value), addr);
225
+	__raw_writel((u32 __force)__cpu_to_le32(value), addr);
233226 	__io_aw();
234227 }
235228 #endif
....@@ -240,7 +233,7 @@
240233 static inline void writeq(u64 value, volatile void __iomem *addr)
241234 {
242235 	__io_bw();
243
-	__raw_writeq(__cpu_to_le64(value), addr);
236
+	__raw_writeq((u64 __force)__cpu_to_le64(value), addr);
244237 	__io_aw();
245238 }
246239 #endif
....@@ -455,56 +448,54 @@
455448 #define IO_SPACE_LIMIT 0xffff
456449 #endif
457450 
458
-#include <linux/logic_pio.h>
459
-
460451 /*
461452  * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
462453  * implemented on hardware that needs an additional delay for I/O accesses to
463454  * take effect.
464455  */
465456 
466
-#ifndef inb
467
-#define inb inb
468
-static inline u8 inb(unsigned long addr)
457
+#if !defined(inb) && !defined(_inb)
458
+#define _inb _inb
459
+static inline u8 _inb(unsigned long addr)
469460 {
470461 	u8 val;
471462 
472463 	__io_pbr();
473464 	val = __raw_readb(PCI_IOBASE + addr);
474
-	__io_par();
465
+	__io_par(val);
475466 	return val;
476467 }
477468 #endif
478469 
479
-#ifndef inw
480
-#define inw inw
481
-static inline u16 inw(unsigned long addr)
470
+#if !defined(inw) && !defined(_inw)
471
+#define _inw _inw
472
+static inline u16 _inw(unsigned long addr)
482473 {
483474 	u16 val;
484475 
485476 	__io_pbr();
486
-	val = __le16_to_cpu(__raw_readw(PCI_IOBASE + addr));
487
-	__io_par();
477
+	val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
478
+	__io_par(val);
488479 	return val;
489480 }
490481 #endif
491482 
492
-#ifndef inl
493
-#define inl inl
494
-static inline u32 inl(unsigned long addr)
483
+#if !defined(inl) && !defined(_inl)
484
+#define _inl _inl
485
+static inline u32 _inl(unsigned long addr)
495486 {
496487 	u32 val;
497488 
498489 	__io_pbr();
499
-	val = __le32_to_cpu(__raw_readl(PCI_IOBASE + addr));
500
-	__io_par();
490
+	val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
491
+	__io_par(val);
501492 	return val;
502493 }
503494 #endif
504495 
505
-#ifndef outb
506
-#define outb outb
507
-static inline void outb(u8 value, unsigned long addr)
496
+#if !defined(outb) && !defined(_outb)
497
+#define _outb _outb
498
+static inline void _outb(u8 value, unsigned long addr)
508499 {
509500 	__io_pbw();
510501 	__raw_writeb(value, PCI_IOBASE + addr);
....@@ -512,24 +503,50 @@
512503 }
513504 #endif
514505 
515
-#ifndef outw
516
-#define outw outw
517
-static inline void outw(u16 value, unsigned long addr)
506
+#if !defined(outw) && !defined(_outw)
507
+#define _outw _outw
508
+static inline void _outw(u16 value, unsigned long addr)
518509 {
519510 	__io_pbw();
520
-	__raw_writew(cpu_to_le16(value), PCI_IOBASE + addr);
511
+	__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
521512 	__io_paw();
522513 }
523514 #endif
524515 
525
-#ifndef outl
526
-#define outl outl
527
-static inline void outl(u32 value, unsigned long addr)
516
+#if !defined(outl) && !defined(_outl)
517
+#define _outl _outl
518
+static inline void _outl(u32 value, unsigned long addr)
528519 {
529520 	__io_pbw();
530
-	__raw_writel(cpu_to_le32(value), PCI_IOBASE + addr);
521
+	__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
531522 	__io_paw();
532523 }
524
+#endif
525
+
526
+#include <linux/logic_pio.h>
527
+
528
+#ifndef inb
529
+#define inb _inb
530
+#endif
531
+
532
+#ifndef inw
533
+#define inw _inw
534
+#endif
535
+
536
+#ifndef inl
537
+#define inl _inl
538
+#endif
539
+
540
+#ifndef outb
541
+#define outb _outb
542
+#endif
543
+
544
+#ifndef outw
545
+#define outw _outw
546
+#endif
547
+
548
+#ifndef outl
549
+#define outl _outl
533550 #endif
534551 
535552 #ifndef inb_p
....@@ -894,18 +911,6 @@
894911 #include <linux/vmalloc.h>
895912 #define __io_virt(x) ((void __force *)(x))
896913 
897
-#ifndef CONFIG_GENERIC_IOMAP
898
-struct pci_dev;
899
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
900
-
901
-#ifndef pci_iounmap
902
-#define pci_iounmap pci_iounmap
903
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
904
-{
905
-}
906
-#endif
907
-#endif /* CONFIG_GENERIC_IOMAP */
908
-
909914 /*
910915  * Change virtual addresses to physical addresses and vv.
911916  * These are pretty trivial
....@@ -929,39 +934,17 @@
929934 /**
930935  * DOC: ioremap() and ioremap_*() variants
931936  *
932
- * If you have an IOMMU your architecture is expected to have both ioremap()
933
- * and iounmap() implemented otherwise the asm-generic helpers will provide a
934
- * direct mapping.
937
+ * Architectures with an MMU are expected to provide ioremap() and iounmap()
938
+ * themselves or rely on GENERIC_IOREMAP.  For NOMMU architectures we provide
939
+ * a default nop-op implementation that expect that the physical address used
940
+ * for MMIO are already marked as uncached, and can be used as kernel virtual
941
+ * addresses.
935942  *
936
- * There are ioremap_*() call variants, if you have no IOMMU we naturally will
937
- * default to direct mapping for all of them, you can override these defaults.
938
- * If you have an IOMMU you are highly encouraged to provide your own
939
- * ioremap variant implementation as there currently is no safe architecture
940
- * agnostic default. To avoid possible improper behaviour default asm-generic
941
- * ioremap_*() variants all return NULL when an IOMMU is available. If you've
942
- * defined your own ioremap_*() variant you must then declare your own
943
- * ioremap_*() variant as defined to itself to avoid the default NULL return.
943
+ * ioremap_wc() and ioremap_wt() can provide more relaxed caching attributes
944
+ * for specific drivers if the architecture choses to implement them.  If they
945
+ * are not implemented we fall back to plain ioremap.
944946  */
945
-
946
-#ifdef CONFIG_MMU
947
-
948
-#ifndef ioremap_uc
949
-#define ioremap_uc ioremap_uc
950
-static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
951
-{
952
-	return NULL;
953
-}
954
-#endif
955
-
956
-#else /* !CONFIG_MMU */
957
-
958
-/*
959
- * Change "struct page" to physical address.
960
- *
961
- * This implementation is for the no-MMU case only... if you have an MMU
962
- * you'll need to provide your own definitions.
963
- */
964
-
947
+#ifndef CONFIG_MMU
965948 #ifndef ioremap
966949 #define ioremap ioremap
967950 static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
....@@ -970,53 +953,45 @@
970953 }
971954 #endif
972955 
973
-#ifndef __ioremap
974
-#define __ioremap __ioremap
975
-static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
976
-				      unsigned long flags)
977
-{
978
-	return ioremap(offset, size);
979
-}
980
-#endif
981
-
982956 #ifndef iounmap
983957 #define iounmap iounmap
984
-
985958 static inline void iounmap(void __iomem *addr)
986959 {
987960 }
988961 #endif
989
-#endif /* CONFIG_MMU */
990
-#ifndef ioremap_nocache
991
-void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
992
-#define ioremap_nocache ioremap_nocache
993
-static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
962
+#elif defined(CONFIG_GENERIC_IOREMAP)
963
+#include <linux/pgtable.h>
964
+
965
+void __iomem *ioremap_prot(phys_addr_t addr, size_t size, unsigned long prot);
966
+void iounmap(volatile void __iomem *addr);
967
+
968
+static inline void __iomem *ioremap(phys_addr_t addr, size_t size)
994969 {
995
-	return ioremap(offset, size);
970
+	/* _PAGE_IOREMAP needs to be supplied by the architecture */
971
+	return ioremap_prot(addr, size, _PAGE_IOREMAP);
996972 }
973
+#endif /* !CONFIG_MMU || CONFIG_GENERIC_IOREMAP */
974
+
975
+#ifndef ioremap_wc
976
+#define ioremap_wc ioremap
997977 #endif
998978 
979
+#ifndef ioremap_wt
980
+#define ioremap_wt ioremap
981
+#endif
982
+
983
+/*
984
+ * ioremap_uc is special in that we do require an explicit architecture
985
+ * implementation.  In general you do not want to use this function in a
986
+ * driver and use plain ioremap, which is uncached by default.  Similarly
987
+ * architectures should not implement it unless they have a very good
988
+ * reason.
989
+ */
999990 #ifndef ioremap_uc
1000991 #define ioremap_uc ioremap_uc
1001992 static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
1002993 {
1003
-	return ioremap_nocache(offset, size);
1004
-}
1005
-#endif
1006
-
1007
-#ifndef ioremap_wc
1008
-#define ioremap_wc ioremap_wc
1009
-static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
1010
-{
1011
-	return ioremap_nocache(offset, size);
1012
-}
1013
-#endif
1014
-
1015
-#ifndef ioremap_wt
1016
-#define ioremap_wt ioremap_wt
1017
-static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size)
1018
-{
1019
-	return ioremap_nocache(offset, size);
994
+	return NULL;
1020995 }
1021996 #endif
1022997 
....@@ -1028,6 +1003,16 @@
10281003 {
10291004 	port &= IO_SPACE_LIMIT;
10301005 	return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
1006
+}
1007
+#define __pci_ioport_unmap __pci_ioport_unmap
1008
+static inline void __pci_ioport_unmap(void __iomem *p)
1009
+{
1010
+	uintptr_t start = (uintptr_t) PCI_IOBASE;
1011
+	uintptr_t addr = (uintptr_t) p;
1012
+
1013
+	if (addr >= start && addr < start + IO_SPACE_LIMIT)
1014
+		return;
1015
+	iounmap(p);
10311016 }
10321017 #endif
10331018 
....@@ -1043,6 +1028,23 @@
10431028 #endif /* CONFIG_GENERIC_IOMAP */
10441029 #endif /* CONFIG_HAS_IOPORT_MAP */
10451030 
1031
+#ifndef CONFIG_GENERIC_IOMAP
1032
+struct pci_dev;
1033
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
1034
+
1035
+#ifndef __pci_ioport_unmap
1036
+static inline void __pci_ioport_unmap(void __iomem *p) {}
1037
+#endif
1038
+
1039
+#ifndef pci_iounmap
1040
+#define pci_iounmap pci_iounmap
1041
+static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
1042
+{
1043
+	__pci_ioport_unmap(p);
1044
+}
1045
+#endif
1046
+#endif /* CONFIG_GENERIC_IOMAP */
1047
+
10461048 /*
10471049  * Convert a virtual cached pointer to an uncached pointer
10481050  */