~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,6 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/************************************************************************
2	3	* Linux driver for *
3		- * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
	4	+ * ICP vortex GmbH: GDT PCI Disk Array Controllers *
4	5	* Intel Corporation: Storage RAID Controllers *
5	6	* *
6	7	* gdth.c *
..	..	@@ -13,33 +14,15 @@
13	14	* Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14	15	* Johannes Dinner <johannes_dinner@adaptec.com> *
15	16	* *
16		- * This program is free software; you can redistribute it and/or modify *
17		- * it under the terms of the GNU General Public License as published *
18		- * by the Free Software Foundation; either version 2 of the License, *
19		- * or (at your option) any later version. *
20		- * *
21		- * This program is distributed in the hope that it will be useful, *
22		- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24		- * GNU General Public License for more details. *
25		- * *
26		- * You should have received a copy of the GNU General Public License *
27		- * along with this kernel; if not, write to the Free Software *
28		- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29	17	* *
30	18	* Linux kernel 2.6.x supported *
31	19	* *
32	20	************************************************************************/
33	21
34	22	/* All GDT Disk Array Controllers are fully supported by this driver.
35		- * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
	23	+ * This includes the PCI SCSI Disk Array Controllers and the
36	24	* PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37	25	* list of all controller types.
38		- *
39		- * If you have one or more GDT3000/3020 EISA controllers with
40		- * controller BIOS disabled, you have to set the IRQ values with the
41		- * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42		- * the IRQ values for the EISA controllers.
43	26	*
44	27	* After the optional list of IRQ values, other possible
45	28	* command line options are:
..	..	@@ -61,14 +44,12 @@
61	44	* access a shared resource from several nodes,
62	45	* appropriate controller firmware required
63	46	* shared_access:N enable driver reserve/release protocol
64		- * probe_eisa_isa:Y scan for EISA/ISA controllers
65		- * probe_eisa_isa:N do not scan for EISA/ISA controllers
66	47	* force_dma32:Y use only 32 bit DMA mode
67	48	* force_dma32:N use 64 bit DMA mode, if supported
68	49	*
69	50	* The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
70	51	* max_ids:127,rescan:N,hdr_channel:0,
71		- * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
	52	+ * shared_access:Y,force_dma32:N".
72	53	* Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
73	54	*
74	55	* When loading the gdth driver as a module, the same options are available.
..	..	@@ -79,7 +60,7 @@
79	60	*
80	61	* Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
81	62	* max_ids=127 rescan=0 hdr_channel=0 shared_access=0
82		- * probe_eisa_isa=0 force_dma32=0"
	63	+ * force_dma32=0"
83	64	* The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
84	65	*/
85	66
..	..	@@ -95,10 +76,6 @@
95	76	* sent_command: unused
96	77	* phase: unused
97	78	*/
98		-
99		-
100		-/* interrupt coalescing */
101		-/* #define INT_COAL */
102	79
103	80	/* statistics */
104	81	#define GDTH_STATISTICS
..	..	@@ -122,10 +99,6 @@
122	99	#include <linux/list.h>
123	100	#include <linux/mutex.h>
124	101	#include <linux/slab.h>
125		-
126		-#ifdef GDTH_RTC
127		-#include <linux/mc146818rtc.h>
128		-#endif
129	102	#include <linux/reboot.h>
130	103
131	104	#include <asm/dma.h>
..	..	@@ -192,79 +165,9 @@
192	165
193	166	#ifdef DEBUG_GDTH
194	167	static u8 DebugState = DEBUG_GDTH;
195		-
196		-#ifdef __SERIAL__
197		-#define MAX_SERBUF 160
198		-static void ser_init(void);
199		-static void ser_puts(char *str);
200		-static void ser_putc(char c);
201		-static int ser_printk(const char *fmt, ...);
202		-static char strbuf[MAX_SERBUF+1];
203		-#ifdef __COM2__
204		-#define COM_BASE 0x2f8
205		-#else
206		-#define COM_BASE 0x3f8
207		-#endif
208		-static void ser_init()
209		-{
210		- unsigned port=COM_BASE;
211		-
212		- outb(0x80,port+3);
213		- outb(0,port+1);
214		- /* 19200 Baud, if 9600: outb(12,port) */
215		- outb(6, port);
216		- outb(3,port+3);
217		- outb(0,port+1);
218		- /*
219		- ser_putc('I');
220		- ser_putc(' ');
221		- */
222		-}
223		-
224		-static void ser_puts(char *str)
225		-{
226		- char *ptr;
227		-
228		- ser_init();
229		- for (ptr=str;*ptr;++ptr)
230		- ser_putc(*ptr);
231		-}
232		-
233		-static void ser_putc(char c)
234		-{
235		- unsigned port=COM_BASE;
236		-
237		- while ((inb(port+5) & 0x20)==0);
238		- outb(c,port);
239		- if (c==0x0a)
240		- {
241		- while ((inb(port+5) & 0x20)==0);
242		- outb(0x0d,port);
243		- }
244		-}
245		-
246		-static int ser_printk(const char *fmt, ...)
247		-{
248		- va_list args;
249		- int i;
250		-
251		- va_start(args,fmt);
252		- i = vsprintf(strbuf,fmt,args);
253		- ser_puts(strbuf);
254		- va_end(args);
255		- return i;
256		-}
257		-
258		-#define TRACE(a) {if (DebugState==1) {ser_printk a;}}
259		-#define TRACE2(a) {if (DebugState==1 \|\| DebugState==2) {ser_printk a;}}
260		-#define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
261		-
262		-#else /* !__SERIAL__ */
263	168	#define TRACE(a) {if (DebugState==1) {printk a;}}
264	169	#define TRACE2(a) {if (DebugState==1 \|\| DebugState==2) {printk a;}}
265	170	#define TRACE3(a) {if (DebugState!=0) {printk a;}}
266		-#endif
267		-
268	171	#else /* !DEBUG */
269	172	#define TRACE(a)
270	173	#define TRACE2(a)
..	..	@@ -273,9 +176,6 @@
273	176
274	177	#ifdef GDTH_STATISTICS
275	178	static u32 max_rq=0, max_index=0, max_sg=0;
276		-#ifdef INT_COAL
277		-static u32 max_int_coal=0;
278		-#endif
279	179	static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
280	180	static struct timer_list gdth_timer;
281	181	#endif
..	..	@@ -286,12 +186,6 @@
286	186
287	187	#define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
288	188
289		-#ifdef CONFIG_ISA
290		-static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
291		-#endif
292		-#if defined(CONFIG_EISA) \|\| defined(CONFIG_ISA)
293		-static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
294		-#endif
295	189	static u8 gdth_polling; /* polling if TRUE */
296	190	static int gdth_ctr_count = 0; /* controller count */
297	191	static LIST_HEAD(gdth_instances); /* controller list */
..	..	@@ -325,10 +219,6 @@
325	219	};
326	220
327	221	/* LILO and modprobe/insmod parameters */
328		-/* IRQ list for GDT3000/3020 EISA controllers */
329		-static int irq[MAXHA] __initdata =
330		-{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
331		- 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
332	222	/* disable driver flag */
333	223	static int disable __initdata = 0;
334	224	/* reserve flag */
..	..	@@ -348,13 +238,10 @@
348	238	static int rescan = 0;
349	239	/* shared access */
350	240	static int shared_access = 1;
351		-/* enable support for EISA and ISA controllers */
352		-static int probe_eisa_isa = 0;
353	241	/* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
354	242	static int force_dma32 = 0;
355	243
356	244	/* parameters for modprobe/insmod */
357		-module_param_hw_array(irq, int, irq, NULL, 0);
358	245	module_param(disable, int, 0);
359	246	module_param(reserve_mode, int, 0);
360	247	module_param_array(reserve_list, int, NULL, 0);
..	..	@@ -363,7 +250,6 @@
363	250	module_param(max_ids, int, 0);
364	251	module_param(rescan, int, 0);
365	252	module_param(shared_access, int, 0);
366		-module_param(probe_eisa_isa, int, 0);
367	253	module_param(force_dma32, int, 0);
368	254	MODULE_AUTHOR("Achim Leubner");
369	255	MODULE_LICENSE("GPL");
..	..	@@ -443,8 +329,8 @@
443	329	scp->scsi_done(scp);
444	330	}
445	331
446		-int __gdth_execute(struct scsi_device sdev, gdth_cmd_str gdtcmd, char *cmnd,
447		- int timeout, u32 *info)
	332	+static int __gdth_execute(struct scsi_device sdev, gdth_cmd_str gdtcmd,
	333	+ char cmnd, int timeout, u32 info)
448	334	{
449	335	gdth_ha_str *ha = shost_priv(sdev->host);
450	336	struct scsi_cmnd *scp;
..	..	@@ -514,45 +400,6 @@
514	400	}
515	401	}
516	402	}
517		-
518		-/* controller search and initialization functions */
519		-#ifdef CONFIG_EISA
520		-static int __init gdth_search_eisa(u16 eisa_adr)
521		-{
522		- u32 id;
523		-
524		- TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
525		- id = inl(eisa_adr+ID0REG);
526		- if (id == GDT3A_ID \|\| id == GDT3B_ID) { /* GDT3000A or GDT3000B */
527		- if ((inb(eisa_adr+EISAREG) & 8) == 0)
528		- return 0; /* not EISA configured */
529		- return 1;
530		- }
531		- if (id == GDT3_ID) /* GDT3000 */
532		- return 1;
533		-
534		- return 0;
535		-}
536		-#endif /* CONFIG_EISA */
537		-
538		-#ifdef CONFIG_ISA
539		-static int __init gdth_search_isa(u32 bios_adr)
540		-{
541		- void __iomem *addr;
542		- u32 id;
543		-
544		- TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
545		- if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
546		- id = readl(addr);
547		- iounmap(addr);
548		- if (id == GDT2_ID) /* GDT2000 */
549		- return 1;
550		- }
551		- return 0;
552		-}
553		-#endif /* CONFIG_ISA */
554		-
555		-#ifdef CONFIG_PCI
556	403
557	404	static bool gdth_search_vortex(u16 device)
558	405	{
..	..	@@ -656,204 +503,7 @@
656	503
657	504	return 0;
658	505	}
659		-#endif /* CONFIG_PCI */
660	506
661		-#ifdef CONFIG_EISA
662		-static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
663		-{
664		- u32 retries,id;
665		- u8 prot_ver,eisacf,i,irq_found;
666		-
667		- TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
668		-
669		- /* disable board interrupts, deinitialize services */
670		- outb(0xff,eisa_adr+EDOORREG);
671		- outb(0x00,eisa_adr+EDENABREG);
672		- outb(0x00,eisa_adr+EINTENABREG);
673		-
674		- outb(0xff,eisa_adr+LDOORREG);
675		- retries = INIT_RETRIES;
676		- gdth_delay(20);
677		- while (inb(eisa_adr+EDOORREG) != 0xff) {
678		- if (--retries == 0) {
679		- printk("GDT-EISA: Initialization error (DEINIT failed)\n");
680		- return 0;
681		- }
682		- gdth_delay(1);
683		- TRACE2(("wait for DEINIT: retries=%d\n",retries));
684		- }
685		- prot_ver = inb(eisa_adr+MAILBOXREG);
686		- outb(0xff,eisa_adr+EDOORREG);
687		- if (prot_ver != PROTOCOL_VERSION) {
688		- printk("GDT-EISA: Illegal protocol version\n");
689		- return 0;
690		- }
691		- ha->bmic = eisa_adr;
692		- ha->brd_phys = (u32)eisa_adr >> 12;
693		-
694		- outl(0,eisa_adr+MAILBOXREG);
695		- outl(0,eisa_adr+MAILBOXREG+4);
696		- outl(0,eisa_adr+MAILBOXREG+8);
697		- outl(0,eisa_adr+MAILBOXREG+12);
698		-
699		- /* detect IRQ */
700		- if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
701		- ha->oem_id = OEM_ID_ICP;
702		- ha->type = GDT_EISA;
703		- ha->stype = id;
704		- outl(1,eisa_adr+MAILBOXREG+8);
705		- outb(0xfe,eisa_adr+LDOORREG);
706		- retries = INIT_RETRIES;
707		- gdth_delay(20);
708		- while (inb(eisa_adr+EDOORREG) != 0xfe) {
709		- if (--retries == 0) {
710		- printk("GDT-EISA: Initialization error (get IRQ failed)\n");
711		- return 0;
712		- }
713		- gdth_delay(1);
714		- }
715		- ha->irq = inb(eisa_adr+MAILBOXREG);
716		- outb(0xff,eisa_adr+EDOORREG);
717		- TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
718		- /* check the result */
719		- if (ha->irq == 0) {
720		- TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
721		- for (i = 0, irq_found = FALSE;
722		- i < MAXHA && irq[i] != 0xff; ++i) {
723		- if (irq[i]==10 \|\| irq[i]==11 \|\| irq[i]==12 \|\| irq[i]==14) {
724		- irq_found = TRUE;
725		- break;
726		- }
727		- }
728		- if (irq_found) {
729		- ha->irq = irq[i];
730		- irq[i] = 0;
731		- printk("GDT-EISA: Can not detect controller IRQ,\n");
732		- printk("Use IRQ setting from command line (IRQ = %d)\n",
733		- ha->irq);
734		- } else {
735		- printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
736		- printk("the controller BIOS or use command line parameters\n");
737		- return 0;
738		- }
739		- }
740		- } else {
741		- eisacf = inb(eisa_adr+EISAREG) & 7;
742		- if (eisacf > 4) /* level triggered */
743		- eisacf -= 4;
744		- ha->irq = gdth_irq_tab[eisacf];
745		- ha->oem_id = OEM_ID_ICP;
746		- ha->type = GDT_EISA;
747		- ha->stype = id;
748		- }
749		-
750		- ha->dma64_support = 0;
751		- return 1;
752		-}
753		-#endif /* CONFIG_EISA */
754		-
755		-#ifdef CONFIG_ISA
756		-static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
757		-{
758		- register gdt2_dpram_str __iomem *dp2_ptr;
759		- int i;
760		- u8 irq_drq,prot_ver;
761		- u32 retries;
762		-
763		- TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
764		-
765		- ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
766		- if (ha->brd == NULL) {
767		- printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
768		- return 0;
769		- }
770		- dp2_ptr = ha->brd;
771		- writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
772		- /* reset interface area */
773		- memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
774		- if (readl(&dp2_ptr->u) != 0) {
775		- printk("GDT-ISA: Initialization error (DPMEM write error)\n");
776		- iounmap(ha->brd);
777		- return 0;
778		- }
779		-
780		- /* disable board interrupts, read DRQ and IRQ */
781		- writeb(0xff, &dp2_ptr->io.irqdel);
782		- writeb(0x00, &dp2_ptr->io.irqen);
783		- writeb(0x00, &dp2_ptr->u.ic.S_Status);
784		- writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
785		-
786		- irq_drq = readb(&dp2_ptr->io.rq);
787		- for (i=0; i<3; ++i) {
788		- if ((irq_drq & 1)==0)
789		- break;
790		- irq_drq >>= 1;
791		- }
792		- ha->drq = gdth_drq_tab[i];
793		-
794		- irq_drq = readb(&dp2_ptr->io.rq) >> 3;
795		- for (i=1; i<5; ++i) {
796		- if ((irq_drq & 1)==0)
797		- break;
798		- irq_drq >>= 1;
799		- }
800		- ha->irq = gdth_irq_tab[i];
801		-
802		- /* deinitialize services */
803		- writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
804		- writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
805		- writeb(0, &dp2_ptr->io.event);
806		- retries = INIT_RETRIES;
807		- gdth_delay(20);
808		- while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
809		- if (--retries == 0) {
810		- printk("GDT-ISA: Initialization error (DEINIT failed)\n");
811		- iounmap(ha->brd);
812		- return 0;
813		- }
814		- gdth_delay(1);
815		- }
816		- prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
817		- writeb(0, &dp2_ptr->u.ic.Status);
818		- writeb(0xff, &dp2_ptr->io.irqdel);
819		- if (prot_ver != PROTOCOL_VERSION) {
820		- printk("GDT-ISA: Illegal protocol version\n");
821		- iounmap(ha->brd);
822		- return 0;
823		- }
824		-
825		- ha->oem_id = OEM_ID_ICP;
826		- ha->type = GDT_ISA;
827		- ha->ic_all_size = sizeof(dp2_ptr->u);
828		- ha->stype= GDT2_ID;
829		- ha->brd_phys = bios_adr >> 4;
830		-
831		- /* special request to controller BIOS */
832		- writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
833		- writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
834		- writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
835		- writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
836		- writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
837		- writeb(0, &dp2_ptr->io.event);
838		- retries = INIT_RETRIES;
839		- gdth_delay(20);
840		- while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
841		- if (--retries == 0) {
842		- printk("GDT-ISA: Initialization error\n");
843		- iounmap(ha->brd);
844		- return 0;
845		- }
846		- gdth_delay(1);
847		- }
848		- writeb(0, &dp2_ptr->u.ic.Status);
849		- writeb(0xff, &dp2_ptr->io.irqdel);
850		-
851		- ha->dma64_support = 0;
852		- return 1;
853		-}
854		-#endif /* CONFIG_ISA */
855		-
856		-#ifdef CONFIG_PCI
857	507	static int gdth_init_pci(struct pci_dev pdev, gdth_pci_str pcistr,
858	508	gdth_ha_str *ha)
859	509	{
..	..	@@ -1228,30 +878,19 @@
1228	878
1229	879	return 1;
1230	880	}
1231		-#endif /* CONFIG_PCI */
1232	881
1233	882	/* controller protocol functions */
1234	883
1235	884	static void gdth_enable_int(gdth_ha_str *ha)
1236	885	{
1237	886	unsigned long flags;
1238		- gdt2_dpram_str __iomem *dp2_ptr;
1239	887	gdt6_dpram_str __iomem *dp6_ptr;
1240	888	gdt6m_dpram_str __iomem *dp6m_ptr;
1241	889
1242	890	TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1243	891	spin_lock_irqsave(&ha->smp_lock, flags);
1244	892
1245		- if (ha->type == GDT_EISA) {
1246		- outb(0xff, ha->bmic + EDOORREG);
1247		- outb(0xff, ha->bmic + EDENABREG);
1248		- outb(0x01, ha->bmic + EINTENABREG);
1249		- } else if (ha->type == GDT_ISA) {
1250		- dp2_ptr = ha->brd;
1251		- writeb(1, &dp2_ptr->io.irqdel);
1252		- writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1253		- writeb(1, &dp2_ptr->io.irqen);
1254		- } else if (ha->type == GDT_PCI) {
	893	+ if (ha->type == GDT_PCI) {
1255	894	dp6_ptr = ha->brd;
1256	895	writeb(1, &dp6_ptr->io.irqdel);
1257	896	writeb(0, &dp6_ptr->u.ic.Cmd_Index);
..	..	@@ -1275,12 +914,7 @@
1275	914
1276	915	TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
1277	916
1278		- if (ha->type == GDT_EISA)
1279		- IStatus = inb((u16)ha->bmic + EDOORREG);
1280		- else if (ha->type == GDT_ISA)
1281		- IStatus =
1282		- readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1283		- else if (ha->type == GDT_PCI)
	917	+ if (ha->type == GDT_PCI)
1284	918	IStatus =
1285	919	readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1286	920	else if (ha->type == GDT_PCINEW)
..	..	@@ -1298,11 +932,7 @@
1298	932
1299	933	TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1300	934
1301		- if (ha->type == GDT_EISA)
1302		- gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1303		- else if (ha->type == GDT_ISA)
1304		- gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1305		- else if (ha->type == GDT_PCI)
	935	+ if (ha->type == GDT_PCI)
1306	936	gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1307	937	else if (ha->type == GDT_PCINEW)
1308	938	gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
..	..	@@ -1336,11 +966,7 @@
1336	966	{
1337	967	TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1338	968
1339		- if (ha->type == GDT_EISA) {
1340		- outb(1, ha->bmic + SEMA0REG);
1341		- } else if (ha->type == GDT_ISA) {
1342		- writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1343		- } else if (ha->type == GDT_PCI) {
	969	+ if (ha->type == GDT_PCI) {
1344	970	writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1345	971	} else if (ha->type == GDT_PCINEW) {
1346	972	outb(1, PTR2USHORT(&ha->plx->sema0_reg));
..	..	@@ -1356,7 +982,6 @@
1356	982	register gdt6m_dpram_str __iomem *dp6m_ptr;
1357	983	register gdt6c_dpram_str __iomem *dp6c_ptr;
1358	984	gdt6_dpram_str __iomem *dp6_ptr;
1359		- gdt2_dpram_str __iomem *dp2_ptr;
1360	985	u16 cp_count,dp_offset,cmd_no;
1361	986
1362	987	TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
..	..	@@ -1367,8 +992,6 @@
1367	992	cmd_ptr = ha->pccb;
1368	993
1369	994	++ha->cmd_cnt;
1370		- if (ha->type == GDT_EISA)
1371		- return; /* no DPMEM, no copy */
1372	995
1373	996	/* set cpcount dword aligned */
1374	997	if (cp_count & 3)
..	..	@@ -1377,14 +1000,7 @@
1377	1000	ha->cmd_offs_dpmem += cp_count;
1378	1001
1379	1002	/* set offset and service, copy command to DPMEM */
1380		- if (ha->type == GDT_ISA) {
1381		- dp2_ptr = ha->brd;
1382		- writew(dp_offset + DPMEM_COMMAND_OFFSET,
1383		- &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1384		- writew((u16)cmd_ptr->Service,
1385		- &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1386		- memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1387		- } else if (ha->type == GDT_PCI) {
	1003	+ if (ha->type == GDT_PCI) {
1388	1004	dp6_ptr = ha->brd;
1389	1005	writew(dp_offset + DPMEM_COMMAND_OFFSET,
1390	1006	&dp6_ptr->u.ic.comm_queue[cmd_no].offset);
..	..	@@ -1430,13 +1046,7 @@
1430	1046	if (ha->pccb->OpCode == GDT_INIT)
1431	1047	ha->pccb->Service \|= 0x80;
1432	1048
1433		- if (ha->type == GDT_EISA) {
1434		- if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1435		- outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1436		- outb(ha->pccb->Service, ha->bmic + LDOORREG);
1437		- } else if (ha->type == GDT_ISA) {
1438		- writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1439		- } else if (ha->type == GDT_PCI) {
	1049	+ if (ha->type == GDT_PCI) {
1440	1050	writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1441	1051	} else if (ha->type == GDT_PCINEW) {
1442	1052	outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
..	..	@@ -1560,15 +1170,7 @@
1560	1170	gdth_arcdl_str *alst;
1561	1171	gdth_alist_str *alst2;
1562	1172	gdth_oem_str_ioctl *oemstr;
1563		-#ifdef INT_COAL
1564		- gdth_perf_modes *pmod;
1565		-#endif
1566	1173
1567		-#ifdef GDTH_RTC
1568		- u8 rtc[12];
1569		- unsigned long flags;
1570		-#endif
1571		-
1572	1174	TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1573	1175	ok = 0;
1574	1176
..	..	@@ -1588,29 +1190,6 @@
1588	1190	}
1589	1191	TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1590	1192
1591		-#ifdef GDTH_RTC
1592		- /* read realtime clock info, send to controller */
1593		- /* 1. wait for the falling edge of update flag */
1594		- spin_lock_irqsave(&rtc_lock, flags);
1595		- for (j = 0; j < 1000000; ++j)
1596		- if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1597		- break;
1598		- for (j = 0; j < 1000000; ++j)
1599		- if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1600		- break;
1601		- /* 2. read info */
1602		- do {
1603		- for (j = 0; j < 12; ++j)
1604		- rtc[j] = CMOS_READ(j);
1605		- } while (rtc[0] != CMOS_READ(0));
1606		- spin_unlock_irqrestore(&rtc_lock, flags);
1607		- TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",(u32 )&rtc[0],
1608		- (u32 )&rtc[4], (u32 )&rtc[8]));
1609		- /* 3. send to controller firmware */
1610		- gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, (u32 )&rtc[0],
1611		- (u32 )&rtc[4], (u32 )&rtc[8]);
1612		-#endif
1613		-
1614	1193	/* unfreeze all IOs */
1615	1194	gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1616	1195
..	..	@@ -1632,35 +1211,6 @@
1632	1211	TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1633	1212	cdev_cnt = (u16)ha->info;
1634	1213	ha->fw_vers = ha->service;
1635		-
1636		-#ifdef INT_COAL
1637		- if (ha->type == GDT_PCIMPR) {
1638		- /* set perf. modes */
1639		- pmod = (gdth_perf_modes *)ha->pscratch;
1640		- pmod->version = 1;
1641		- pmod->st_mode = 1; /* enable one status buffer */
1642		- ((u64 )&pmod->st_buff_addr1) = ha->coal_stat_phys;
1643		- pmod->st_buff_indx1 = COALINDEX;
1644		- pmod->st_buff_addr2 = 0;
1645		- pmod->st_buff_u_addr2 = 0;
1646		- pmod->st_buff_indx2 = 0;
1647		- pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1648		- pmod->cmd_mode = 0; // disable all cmd buffers
1649		- pmod->cmd_buff_addr1 = 0;
1650		- pmod->cmd_buff_u_addr1 = 0;
1651		- pmod->cmd_buff_indx1 = 0;
1652		- pmod->cmd_buff_addr2 = 0;
1653		- pmod->cmd_buff_u_addr2 = 0;
1654		- pmod->cmd_buff_indx2 = 0;
1655		- pmod->cmd_buff_size = 0;
1656		- pmod->reserved1 = 0;
1657		- pmod->reserved2 = 0;
1658		- if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1659		- INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1660		- printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1661		- }
1662		- }
1663		-#endif
1664	1214
1665	1215	/* detect number of buses - try new IOCTL */
1666	1216	iocr = (gdth_raw_iochan_str *)ha->pscratch;
..	..	@@ -2433,9 +1983,6 @@
2433	1983	TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2434	1984	scp->cmnd[0],scp->cmd_len,hdrive));
2435	1985
2436		- if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2437		- return 0;
2438		-
2439	1986	mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2440	1987	/* test for READ_16, WRITE_16 if !mode64 ? ---
2441	1988	not required, should not occur due to error return on
..	..	@@ -2518,9 +2065,9 @@
2518	2065
2519	2066	if (scsi_bufflen(scp)) {
2520	2067	cmndinfo->dma_dir = (read_write == 1 ?
2521		- PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2522		- sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2523		- cmndinfo->dma_dir);
	2068	+ DMA_TO_DEVICE : DMA_FROM_DEVICE);
	2069	+ sgcnt = dma_map_sg(&ha->pdev->dev, scsi_sglist(scp),
	2070	+ scsi_sg_count(scp), cmndinfo->dma_dir);
2524	2071	if (mode64) {
2525	2072	struct scatterlist *sl;
2526	2073
..	..	@@ -2528,12 +2075,6 @@
2528	2075	cmdp->u.cache64.sg_canz = sgcnt;
2529	2076	scsi_for_each_sg(scp, sl, sgcnt, i) {
2530	2077	cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2531		-#ifdef GDTH_DMA_STATISTICS
2532		- if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
2533		- ha->dma64_cnt++;
2534		- else
2535		- ha->dma32_cnt++;
2536		-#endif
2537	2078	cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2538	2079	}
2539	2080	} else {
..	..	@@ -2543,9 +2084,6 @@
2543	2084	cmdp->u.cache.sg_canz = sgcnt;
2544	2085	scsi_for_each_sg(scp, sl, sgcnt, i) {
2545	2086	cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2546		-#ifdef GDTH_DMA_STATISTICS
2547		- ha->dma32_cnt++;
2548		-#endif
2549	2087	cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2550	2088	}
2551	2089	}
..	..	@@ -2603,8 +2141,6 @@
2603	2141	dma_addr_t sense_paddr;
2604	2142	int cmd_index, sgcnt, mode64;
2605	2143	u8 t,l;
2606		- struct page *page;
2607		- unsigned long offset;
2608	2144	struct gdth_cmndinfo *cmndinfo;
2609	2145
2610	2146	t = scp->device->id;
..	..	@@ -2612,9 +2148,6 @@
2612	2148	cmdp = ha->pccb;
2613	2149	TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2614	2150	scp->cmnd[0],b,t,l));
2615		-
2616		- if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2617		- return 0;
2618	2151
2619	2152	mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2620	2153
..	..	@@ -2649,10 +2182,8 @@
2649	2182	}
2650	2183
2651	2184	} else {
2652		- page = virt_to_page(scp->sense_buffer);
2653		- offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
2654		- sense_paddr = pci_map_page(ha->pdev,page,offset,
2655		- 16,PCI_DMA_FROMDEVICE);
	2185	+ sense_paddr = dma_map_single(&ha->pdev->dev, scp->sense_buffer, 16,
	2186	+ DMA_FROM_DEVICE);
2656	2187
2657	2188	cmndinfo->sense_paddr = sense_paddr;
2658	2189	cmdp->OpCode = GDT_WRITE; /* always */
..	..	@@ -2693,9 +2224,9 @@
2693	2224	}
2694	2225
2695	2226	if (scsi_bufflen(scp)) {
2696		- cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
2697		- sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2698		- cmndinfo->dma_dir);
	2227	+ cmndinfo->dma_dir = DMA_BIDIRECTIONAL;
	2228	+ sgcnt = dma_map_sg(&ha->pdev->dev, scsi_sglist(scp),
	2229	+ scsi_sg_count(scp), cmndinfo->dma_dir);
2699	2230	if (mode64) {
2700	2231	struct scatterlist *sl;
2701	2232
..	..	@@ -2703,12 +2234,6 @@
2703	2234	cmdp->u.raw64.sg_ranz = sgcnt;
2704	2235	scsi_for_each_sg(scp, sl, sgcnt, i) {
2705	2236	cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2706		-#ifdef GDTH_DMA_STATISTICS
2707		- if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
2708		- ha->dma64_cnt++;
2709		- else
2710		- ha->dma32_cnt++;
2711		-#endif
2712	2237	cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2713	2238	}
2714	2239	} else {
..	..	@@ -2718,9 +2243,6 @@
2718	2243	cmdp->u.raw.sg_ranz = sgcnt;
2719	2244	scsi_for_each_sg(scp, sl, sgcnt, i) {
2720	2245	cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2721		-#ifdef GDTH_DMA_STATISTICS
2722		- ha->dma32_cnt++;
2723		-#endif
2724	2246	cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2725	2247	}
2726	2248	}
..	..	@@ -2777,9 +2299,6 @@
2777	2299
2778	2300	cmdp= ha->pccb;
2779	2301	TRACE2(("gdth_special_cmd(): "));
2780		-
2781		- if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2782		- return 0;
2783	2302
2784	2303	cmdp = cmndinfo->internal_cmd_str;
2785	2304	cmdp->RequestBuffer = scp;
..	..	@@ -2959,18 +2478,11 @@
2959	2478	{
2960	2479	gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
2961	2480	gdt6_dpram_str __iomem *dp6_ptr;
2962		- gdt2_dpram_str __iomem *dp2_ptr;
2963	2481	struct scsi_cmnd *scp;
2964	2482	int rval, i;
2965	2483	u8 IStatus;
2966	2484	u16 Service;
2967	2485	unsigned long flags = 0;
2968		-#ifdef INT_COAL
2969		- int coalesced = FALSE;
2970		- int next = FALSE;
2971		- gdth_coal_status *pcs = NULL;
2972		- int act_int_coal = 0;
2973		-#endif
2974	2486
2975	2487	TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
2976	2488
..	..	@@ -2997,53 +2509,7 @@
2997	2509	++act_ints;
2998	2510	#endif
2999	2511
3000		-#ifdef INT_COAL
3001		- /* See if the fw is returning coalesced status */
3002		- if (IStatus == COALINDEX) {
3003		- /* Coalesced status. Setup the initial status
3004		- buffer pointer and flags */
3005		- pcs = ha->coal_stat;
3006		- coalesced = TRUE;
3007		- next = TRUE;
3008		- }
3009		-
3010		- do {
3011		- if (coalesced) {
3012		- /* For coalesced requests all status
3013		- information is found in the status buffer */
3014		- IStatus = (u8)(pcs->status & 0xff);
3015		- }
3016		-#endif
3017		-
3018		- if (ha->type == GDT_EISA) {
3019		- if (IStatus & 0x80) { /* error flag */
3020		- IStatus &= ~0x80;
3021		- ha->status = inw(ha->bmic + MAILBOXREG+8);
3022		- TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3023		- } else /* no error */
3024		- ha->status = S_OK;
3025		- ha->info = inl(ha->bmic + MAILBOXREG+12);
3026		- ha->service = inw(ha->bmic + MAILBOXREG+10);
3027		- ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3028		-
3029		- outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3030		- outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3031		- } else if (ha->type == GDT_ISA) {
3032		- dp2_ptr = ha->brd;
3033		- if (IStatus & 0x80) { /* error flag */
3034		- IStatus &= ~0x80;
3035		- ha->status = readw(&dp2_ptr->u.ic.Status);
3036		- TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3037		- } else /* no error */
3038		- ha->status = S_OK;
3039		- ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3040		- ha->service = readw(&dp2_ptr->u.ic.Service);
3041		- ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3042		-
3043		- writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3044		- writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3045		- writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3046		- } else if (ha->type == GDT_PCI) {
	2512	+ if (ha->type == GDT_PCI) {
3047	2513	dp6_ptr = ha->brd;
3048	2514	if (IStatus & 0x80) { /* error flag */
3049	2515	IStatus &= ~0x80;
..	..	@@ -3075,28 +2541,15 @@
3075	2541	dp6m_ptr = ha->brd;
3076	2542	if (IStatus & 0x80) { /* error flag */
3077	2543	IStatus &= ~0x80;
3078		-#ifdef INT_COAL
3079		- if (coalesced)
3080		- ha->status = pcs->ext_status & 0xffff;
3081		- else
3082		-#endif
3083		- ha->status = readw(&dp6m_ptr->i960r.status);
	2544	+ ha->status = readw(&dp6m_ptr->i960r.status);
3084	2545	TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3085	2546	} else /* no error */
3086	2547	ha->status = S_OK;
3087		-#ifdef INT_COAL
3088		- /* get information */
3089		- if (coalesced) {
3090		- ha->info = pcs->info0;
3091		- ha->info2 = pcs->info1;
3092		- ha->service = (pcs->ext_status >> 16) & 0xffff;
3093		- } else
3094		-#endif
3095		- {
3096		- ha->info = readl(&dp6m_ptr->i960r.info[0]);
3097		- ha->service = readw(&dp6m_ptr->i960r.service);
3098		- ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3099		- }
	2548	+
	2549	+ ha->info = readl(&dp6m_ptr->i960r.info[0]);
	2550	+ ha->service = readw(&dp6m_ptr->i960r.service);
	2551	+ ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
	2552	+
3100	2553	/* event string */
3101	2554	if (IStatus == ASYNCINDEX) {
3102	2555	if (ha->service != SCREENSERVICE &&
..	..	@@ -3111,15 +2564,8 @@
3111	2564	}
3112	2565	}
3113	2566	}
3114		-#ifdef INT_COAL
3115		- /* Make sure that non coalesced interrupts get cleared
3116		- before being handled by gdth_async_event/gdth_sync_event */
3117		- if (!coalesced)
3118		-#endif
3119		- {
3120		- writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3121		- writeb(0, &dp6m_ptr->i960r.sema1_reg);
3122		- }
	2567	+ writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
	2568	+ writeb(0, &dp6m_ptr->i960r.sema1_reg);
3123	2569	} else {
3124	2570	TRACE2(("gdth_interrupt() unknown controller type\n"));
3125	2571	if (!gdth_polling)
..	..	@@ -3181,31 +2627,6 @@
3181	2627	} else if (rval == 1) {
3182	2628	gdth_scsi_done(scp);
3183	2629	}
3184		-
3185		-#ifdef INT_COAL
3186		- if (coalesced) {
3187		- /* go to the next status in the status buffer */
3188		- ++pcs;
3189		-#ifdef GDTH_STATISTICS
3190		- ++act_int_coal;
3191		- if (act_int_coal > max_int_coal) {
3192		- max_int_coal = act_int_coal;
3193		- printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
3194		- }
3195		-#endif
3196		- /* see if there is another status */
3197		- if (pcs->status == 0)
3198		- /* Stop the coalesce loop */
3199		- next = FALSE;
3200		- }
3201		- } while (next);
3202		-
3203		- /* coalescing only for new GDT_PCIMPR controllers available */
3204		- if (ha->type == GDT_PCIMPR && coalesced) {
3205		- writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3206		- writeb(0, &dp6m_ptr->i960r.sema1_reg);
3207		- }
3208		-#endif
3209	2630
3210	2631	gdth_next(ha);
3211	2632	return IRQ_HANDLED;
..	..	@@ -3313,12 +2734,12 @@
3313	2734	return 2;
3314	2735	}
3315	2736	if (scsi_bufflen(scp))
3316		- pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
	2737	+ dma_unmap_sg(&ha->pdev->dev, scsi_sglist(scp), scsi_sg_count(scp),
3317	2738	cmndinfo->dma_dir);
3318	2739
3319	2740	if (cmndinfo->sense_paddr)
3320		- pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3321		- PCI_DMA_FROMDEVICE);
	2741	+ dma_unmap_page(&ha->pdev->dev, cmndinfo->sense_paddr, 16,
	2742	+ DMA_FROM_DEVICE);
3322	2743
3323	2744	if (ha->status == S_OK) {
3324	2745	cmndinfo->status = S_OK;
..	..	@@ -3586,7 +3007,6 @@
3586	3007	static int gdth_async_event(gdth_ha_str *ha)
3587	3008	{
3588	3009	gdth_cmd_str *cmdp;
3589		- int cmd_index;
3590	3010
3591	3011	cmdp= ha->pccb;
3592	3012	TRACE2(("gdth_async_event() ha %d serv %d\n",
..	..	@@ -3598,7 +3018,6 @@
3598	3018	gdth_delay(0);
3599	3019	cmdp->Service = SCREENSERVICE;
3600	3020	cmdp->RequestBuffer = SCREEN_CMND;
3601		- cmd_index = gdth_get_cmd_index(ha);
3602	3021	gdth_set_sema0(ha);
3603	3022	cmdp->OpCode = GDT_READ;
3604	3023	cmdp->BoardNode = LOCALBOARD;
..	..	@@ -3610,12 +3029,7 @@
3610	3029	+ sizeof(u64);
3611	3030	ha->cmd_cnt = 0;
3612	3031	gdth_copy_command(ha);
3613		- if (ha->type == GDT_EISA)
3614		- printk("[EISA slot %d] ",(u16)ha->brd_phys);
3615		- else if (ha->type == GDT_ISA)
3616		- printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
3617		- else
3618		- printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
	3032	+ printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
3619	3033	(u16)((ha->brd_phys>>3)&0x1f));
3620	3034	gdth_release_event(ha);
3621	3035	}
..	..	@@ -3754,111 +3168,12 @@
3754	3168	}
3755	3169	#endif
3756	3170
3757		-static void __init internal_setup(char str,int ints)
3758		-{
3759		- int i, argc;
3760		- char cur_str, argv;
3761		-
3762		- TRACE2(("internal_setup() str %s ints[0] %d\n",
3763		- str ? str:"NULL", ints ? ints[0]:0));
3764		-
3765		- /* read irq[] from ints[] */
3766		- if (ints) {
3767		- argc = ints[0];
3768		- if (argc > 0) {
3769		- if (argc > MAXHA)
3770		- argc = MAXHA;
3771		- for (i = 0; i < argc; ++i)
3772		- irq[i] = ints[i+1];
3773		- }
3774		- }
3775		-
3776		- /* analyse string */
3777		- argv = str;
3778		- while (argv && (cur_str = strchr(argv, ':'))) {
3779		- int val = 0, c = *++cur_str;
3780		-
3781		- if (c == 'n' \|\| c == 'N')
3782		- val = 0;
3783		- else if (c == 'y' \|\| c == 'Y')
3784		- val = 1;
3785		- else
3786		- val = (int)simple_strtoul(cur_str, NULL, 0);
3787		-
3788		- if (!strncmp(argv, "disable:", 8))
3789		- disable = val;
3790		- else if (!strncmp(argv, "reserve_mode:", 13))
3791		- reserve_mode = val;
3792		- else if (!strncmp(argv, "reverse_scan:", 13))
3793		- reverse_scan = val;
3794		- else if (!strncmp(argv, "hdr_channel:", 12))
3795		- hdr_channel = val;
3796		- else if (!strncmp(argv, "max_ids:", 8))
3797		- max_ids = val;
3798		- else if (!strncmp(argv, "rescan:", 7))
3799		- rescan = val;
3800		- else if (!strncmp(argv, "shared_access:", 14))
3801		- shared_access = val;
3802		- else if (!strncmp(argv, "probe_eisa_isa:", 15))
3803		- probe_eisa_isa = val;
3804		- else if (!strncmp(argv, "reserve_list:", 13)) {
3805		- reserve_list[0] = val;
3806		- for (i = 1; i < MAX_RES_ARGS; i++) {
3807		- cur_str = strchr(cur_str, ',');
3808		- if (!cur_str)
3809		- break;
3810		- if (!isdigit((int)*++cur_str)) {
3811		- --cur_str;
3812		- break;
3813		- }
3814		- reserve_list[i] =
3815		- (int)simple_strtoul(cur_str, NULL, 0);
3816		- }
3817		- if (!cur_str)
3818		- break;
3819		- argv = ++cur_str;
3820		- continue;
3821		- }
3822		-
3823		- if ((argv = strchr(argv, ',')))
3824		- ++argv;
3825		- }
3826		-}
3827		-
3828		-int __init option_setup(char *str)
3829		-{
3830		- int ints[MAXHA];
3831		- char *cur = str;
3832		- int i = 1;
3833		-
3834		- TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3835		-
3836		- while (cur && isdigit(*cur) && i < MAXHA) {
3837		- ints[i++] = simple_strtoul(cur, NULL, 0);
3838		- if ((cur = strchr(cur, ',')) != NULL) cur++;
3839		- }
3840		-
3841		- ints[0] = i - 1;
3842		- internal_setup(cur, ints);
3843		- return 1;
3844		-}
3845	3171
3846	3172	static const char gdth_ctr_name(gdth_ha_str ha)
3847	3173	{
3848	3174	TRACE2(("gdth_ctr_name()\n"));
3849	3175
3850		- if (ha->type == GDT_EISA) {
3851		- switch (ha->stype) {
3852		- case GDT3_ID:
3853		- return("GDT3000/3020");
3854		- case GDT3A_ID:
3855		- return("GDT3000A/3020A/3050A");
3856		- case GDT3B_ID:
3857		- return("GDT3000B/3010A");
3858		- }
3859		- } else if (ha->type == GDT_ISA) {
3860		- return("GDT2000/2020");
3861		- } else if (ha->type == GDT_PCI) {
	3176	+ if (ha->type == GDT_PCI) {
3862	3177	switch (ha->pdev->device) {
3863	3178	case PCI_DEVICE_ID_VORTEX_GDT60x0:
3864	3179	return("GDT6000/6020/6050");
..	..	@@ -4155,131 +3470,148 @@
4155	3470	return 0;
4156	3471	}
4157	3472
	3473	+static void gdth_ioc_cacheservice(gdth_ha_str ha, gdth_ioctl_general gen,
	3474	+ u64 paddr)
	3475	+{
	3476	+ if (ha->cache_feat & GDT_64BIT) {
	3477	+ /* copy elements from 32-bit IOCTL structure */
	3478	+ gen->command.u.cache64.BlockCnt = gen->command.u.cache.BlockCnt;
	3479	+ gen->command.u.cache64.BlockNo = gen->command.u.cache.BlockNo;
	3480	+ gen->command.u.cache64.DeviceNo = gen->command.u.cache.DeviceNo;
	3481	+
	3482	+ if (ha->cache_feat & SCATTER_GATHER) {
	3483	+ gen->command.u.cache64.DestAddr = (u64)-1;
	3484	+ gen->command.u.cache64.sg_canz = 1;
	3485	+ gen->command.u.cache64.sg_lst[0].sg_ptr = paddr;
	3486	+ gen->command.u.cache64.sg_lst[0].sg_len = gen->data_len;
	3487	+ gen->command.u.cache64.sg_lst[1].sg_len = 0;
	3488	+ } else {
	3489	+ gen->command.u.cache64.DestAddr = paddr;
	3490	+ gen->command.u.cache64.sg_canz = 0;
	3491	+ }
	3492	+ } else {
	3493	+ if (ha->cache_feat & SCATTER_GATHER) {
	3494	+ gen->command.u.cache.DestAddr = 0xffffffff;
	3495	+ gen->command.u.cache.sg_canz = 1;
	3496	+ gen->command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
	3497	+ gen->command.u.cache.sg_lst[0].sg_len = gen->data_len;
	3498	+ gen->command.u.cache.sg_lst[1].sg_len = 0;
	3499	+ } else {
	3500	+ gen->command.u.cache.DestAddr = paddr;
	3501	+ gen->command.u.cache.sg_canz = 0;
	3502	+ }
	3503	+ }
	3504	+}
	3505	+
	3506	+static void gdth_ioc_scsiraw(gdth_ha_str ha, gdth_ioctl_general gen,
	3507	+ u64 paddr)
	3508	+{
	3509	+ if (ha->raw_feat & GDT_64BIT) {
	3510	+ /* copy elements from 32-bit IOCTL structure */
	3511	+ char cmd[16];
	3512	+
	3513	+ gen->command.u.raw64.sense_len = gen->command.u.raw.sense_len;
	3514	+ gen->command.u.raw64.bus = gen->command.u.raw.bus;
	3515	+ gen->command.u.raw64.lun = gen->command.u.raw.lun;
	3516	+ gen->command.u.raw64.target = gen->command.u.raw.target;
	3517	+ memcpy(cmd, gen->command.u.raw.cmd, 16);
	3518	+ memcpy(gen->command.u.raw64.cmd, cmd, 16);
	3519	+ gen->command.u.raw64.clen = gen->command.u.raw.clen;
	3520	+ gen->command.u.raw64.sdlen = gen->command.u.raw.sdlen;
	3521	+ gen->command.u.raw64.direction = gen->command.u.raw.direction;
	3522	+
	3523	+ /* addresses */
	3524	+ if (ha->raw_feat & SCATTER_GATHER) {
	3525	+ gen->command.u.raw64.sdata = (u64)-1;
	3526	+ gen->command.u.raw64.sg_ranz = 1;
	3527	+ gen->command.u.raw64.sg_lst[0].sg_ptr = paddr;
	3528	+ gen->command.u.raw64.sg_lst[0].sg_len = gen->data_len;
	3529	+ gen->command.u.raw64.sg_lst[1].sg_len = 0;
	3530	+ } else {
	3531	+ gen->command.u.raw64.sdata = paddr;
	3532	+ gen->command.u.raw64.sg_ranz = 0;
	3533	+ }
	3534	+
	3535	+ gen->command.u.raw64.sense_data = paddr + gen->data_len;
	3536	+ } else {
	3537	+ if (ha->raw_feat & SCATTER_GATHER) {
	3538	+ gen->command.u.raw.sdata = 0xffffffff;
	3539	+ gen->command.u.raw.sg_ranz = 1;
	3540	+ gen->command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
	3541	+ gen->command.u.raw.sg_lst[0].sg_len = gen->data_len;
	3542	+ gen->command.u.raw.sg_lst[1].sg_len = 0;
	3543	+ } else {
	3544	+ gen->command.u.raw.sdata = paddr;
	3545	+ gen->command.u.raw.sg_ranz = 0;
	3546	+ }
	3547	+
	3548	+ gen->command.u.raw.sense_data = (u32)paddr + gen->data_len;
	3549	+ }
	3550	+}
	3551	+
4158	3552	static int ioc_general(void __user arg, char cmnd)
4159	3553	{
4160		- gdth_ioctl_general gen;
4161		- char *buf = NULL;
4162		- u64 paddr;
4163		- gdth_ha_str *ha;
4164		- int rval;
	3554	+ gdth_ioctl_general gen;
	3555	+ gdth_ha_str *ha;
	3556	+ char *buf = NULL;
	3557	+ dma_addr_t paddr;
	3558	+ int rval;
4165	3559
4166		- if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4167		- return -EFAULT;
4168		- ha = gdth_find_ha(gen.ionode);
4169		- if (!ha)
4170		- return -EFAULT;
	3560	+ if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
	3561	+ return -EFAULT;
	3562	+ ha = gdth_find_ha(gen.ionode);
	3563	+ if (!ha)
	3564	+ return -EFAULT;
4171	3565
4172		- if (gen.data_len > INT_MAX)
4173		- return -EINVAL;
4174		- if (gen.sense_len > INT_MAX)
4175		- return -EINVAL;
4176		- if (gen.data_len + gen.sense_len > INT_MAX)
4177		- return -EINVAL;
	3566	+ if (gen.data_len > INT_MAX)
	3567	+ return -EINVAL;
	3568	+ if (gen.sense_len > INT_MAX)
	3569	+ return -EINVAL;
	3570	+ if (gen.data_len + gen.sense_len > INT_MAX)
	3571	+ return -EINVAL;
4178	3572
4179		- if (gen.data_len + gen.sense_len != 0) {
4180		- if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
4181		- FALSE, &paddr)))
4182		- return -EFAULT;
4183		- if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4184		- gen.data_len + gen.sense_len)) {
4185		- gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4186		- return -EFAULT;
4187		- }
	3573	+ if (gen.data_len + gen.sense_len > 0) {
	3574	+ buf = dma_alloc_coherent(&ha->pdev->dev,
	3575	+ gen.data_len + gen.sense_len, &paddr,
	3576	+ GFP_KERNEL);
	3577	+ if (!buf)
	3578	+ return -EFAULT;
4188	3579
4189		- if (gen.command.OpCode == GDT_IOCTL) {
4190		- gen.command.u.ioctl.p_param = paddr;
4191		- } else if (gen.command.Service == CACHESERVICE) {
4192		- if (ha->cache_feat & GDT_64BIT) {
4193		- /* copy elements from 32-bit IOCTL structure */
4194		- gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4195		- gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4196		- gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4197		- /* addresses */
4198		- if (ha->cache_feat & SCATTER_GATHER) {
4199		- gen.command.u.cache64.DestAddr = (u64)-1;
4200		- gen.command.u.cache64.sg_canz = 1;
4201		- gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4202		- gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4203		- gen.command.u.cache64.sg_lst[1].sg_len = 0;
4204		- } else {
4205		- gen.command.u.cache64.DestAddr = paddr;
4206		- gen.command.u.cache64.sg_canz = 0;
4207		- }
4208		- } else {
4209		- if (ha->cache_feat & SCATTER_GATHER) {
4210		- gen.command.u.cache.DestAddr = 0xffffffff;
4211		- gen.command.u.cache.sg_canz = 1;
4212		- gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
4213		- gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4214		- gen.command.u.cache.sg_lst[1].sg_len = 0;
4215		- } else {
4216		- gen.command.u.cache.DestAddr = paddr;
4217		- gen.command.u.cache.sg_canz = 0;
4218		- }
4219		- }
4220		- } else if (gen.command.Service == SCSIRAWSERVICE) {
4221		- if (ha->raw_feat & GDT_64BIT) {
4222		- /* copy elements from 32-bit IOCTL structure */
4223		- char cmd[16];
4224		- gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4225		- gen.command.u.raw64.bus = gen.command.u.raw.bus;
4226		- gen.command.u.raw64.lun = gen.command.u.raw.lun;
4227		- gen.command.u.raw64.target = gen.command.u.raw.target;
4228		- memcpy(cmd, gen.command.u.raw.cmd, 16);
4229		- memcpy(gen.command.u.raw64.cmd, cmd, 16);
4230		- gen.command.u.raw64.clen = gen.command.u.raw.clen;
4231		- gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4232		- gen.command.u.raw64.direction = gen.command.u.raw.direction;
4233		- /* addresses */
4234		- if (ha->raw_feat & SCATTER_GATHER) {
4235		- gen.command.u.raw64.sdata = (u64)-1;
4236		- gen.command.u.raw64.sg_ranz = 1;
4237		- gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4238		- gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4239		- gen.command.u.raw64.sg_lst[1].sg_len = 0;
4240		- } else {
4241		- gen.command.u.raw64.sdata = paddr;
4242		- gen.command.u.raw64.sg_ranz = 0;
4243		- }
4244		- gen.command.u.raw64.sense_data = paddr + gen.data_len;
4245		- } else {
4246		- if (ha->raw_feat & SCATTER_GATHER) {
4247		- gen.command.u.raw.sdata = 0xffffffff;
4248		- gen.command.u.raw.sg_ranz = 1;
4249		- gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
4250		- gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4251		- gen.command.u.raw.sg_lst[1].sg_len = 0;
4252		- } else {
4253		- gen.command.u.raw.sdata = paddr;
4254		- gen.command.u.raw.sg_ranz = 0;
4255		- }
4256		- gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
4257		- }
4258		- } else {
4259		- gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4260		- return -EFAULT;
4261		- }
4262		- }
	3580	+ rval = -EFAULT;
	3581	+ if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
	3582	+ gen.data_len + gen.sense_len))
	3583	+ goto out_free_buf;
4263	3584
4264		- rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4265		- if (rval < 0) {
4266		- gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4267		- return rval;
4268		- }
4269		- gen.status = rval;
	3585	+ if (gen.command.OpCode == GDT_IOCTL)
	3586	+ gen.command.u.ioctl.p_param = paddr;
	3587	+ else if (gen.command.Service == CACHESERVICE)
	3588	+ gdth_ioc_cacheservice(ha, &gen, paddr);
	3589	+ else if (gen.command.Service == SCSIRAWSERVICE)
	3590	+ gdth_ioc_scsiraw(ha, &gen, paddr);
	3591	+ else
	3592	+ goto out_free_buf;
	3593	+ }
4270	3594
4271		- if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4272		- gen.data_len + gen.sense_len)) {
4273		- gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4274		- return -EFAULT;
4275		- }
4276		- if (copy_to_user(arg, &gen,
4277		- sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4278		- gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4279		- return -EFAULT;
4280		- }
4281		- gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4282		- return 0;
	3595	+ rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout,
	3596	+ &gen.info);
	3597	+ if (rval < 0)
	3598	+ goto out_free_buf;
	3599	+ gen.status = rval;
	3600	+
	3601	+ rval = -EFAULT;
	3602	+ if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
	3603	+ gen.data_len + gen.sense_len))
	3604	+ goto out_free_buf;
	3605	+ if (copy_to_user(arg, &gen,
	3606	+ sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str)))
	3607	+ goto out_free_buf;
	3608	+
	3609	+ rval = 0;
	3610	+out_free_buf:
	3611	+ if (buf)
	3612	+ dma_free_coherent(&ha->pdev->dev, gen.data_len + gen.sense_len,
	3613	+ buf, paddr);
	3614	+ return rval;
4283	3615	}
4284	3616
4285	3617	static int ioc_hdrlist(void __user arg, char cmnd)
..	..	@@ -4514,22 +3846,17 @@
4514	3846	(NULL == (ha = gdth_find_ha(ctrt.ionode))))
4515	3847	return -EFAULT;
4516	3848
4517		- if (ha->type == GDT_ISA \|\| ha->type == GDT_EISA) {
4518		- ctrt.type = (u8)((ha->stype>>20) - 0x10);
	3849	+ if (ha->type != GDT_PCIMPR) {
	3850	+ ctrt.type = (u8)((ha->stype<<4) + 6);
4519	3851	} else {
4520		- if (ha->type != GDT_PCIMPR) {
4521		- ctrt.type = (u8)((ha->stype<<4) + 6);
4522		- } else {
4523		- ctrt.type =
4524		- (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4525		- if (ha->stype >= 0x300)
4526		- ctrt.ext_type = 0x6000 \| ha->pdev->subsystem_device;
4527		- else
4528		- ctrt.ext_type = 0x6000 \| ha->stype;
4529		- }
4530		- ctrt.device_id = ha->pdev->device;
4531		- ctrt.sub_device_id = ha->pdev->subsystem_device;
	3852	+ ctrt.type = (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
	3853	+ if (ha->stype >= 0x300)
	3854	+ ctrt.ext_type = 0x6000 \| ha->pdev->subsystem_device;
	3855	+ else
	3856	+ ctrt.ext_type = 0x6000 \| ha->stype;
4532	3857	}
	3858	+ ctrt.device_id = ha->pdev->device;
	3859	+ ctrt.sub_device_id = ha->pdev->subsystem_device;
4533	3860	ctrt.info = ha->brd_phys;
4534	3861	ctrt.oem_id = ha->oem_id;
4535	3862	if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
..	..	@@ -4680,276 +4007,9 @@
4680	4007	.sg_tablesize = GDTH_MAXSG,
4681	4008	.cmd_per_lun = GDTH_MAXC_P_L,
4682	4009	.unchecked_isa_dma = 1,
4683		- .use_clustering = ENABLE_CLUSTERING,
4684	4010	.no_write_same = 1,
4685	4011	};
4686	4012
4687		-#ifdef CONFIG_ISA
4688		-static int __init gdth_isa_probe_one(u32 isa_bios)
4689		-{
4690		- struct Scsi_Host *shp;
4691		- gdth_ha_str *ha;
4692		- dma_addr_t scratch_dma_handle = 0;
4693		- int error, i;
4694		-
4695		- if (!gdth_search_isa(isa_bios))
4696		- return -ENXIO;
4697		-
4698		- shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4699		- if (!shp)
4700		- return -ENOMEM;
4701		- ha = shost_priv(shp);
4702		-
4703		- error = -ENODEV;
4704		- if (!gdth_init_isa(isa_bios,ha))
4705		- goto out_host_put;
4706		-
4707		- /* controller found and initialized */
4708		- printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4709		- isa_bios, ha->irq, ha->drq);
4710		-
4711		- error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
4712		- if (error) {
4713		- printk("GDT-ISA: Unable to allocate IRQ\n");
4714		- goto out_host_put;
4715		- }
4716		-
4717		- error = request_dma(ha->drq, "gdth");
4718		- if (error) {
4719		- printk("GDT-ISA: Unable to allocate DMA channel\n");
4720		- goto out_free_irq;
4721		- }
4722		-
4723		- set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4724		- enable_dma(ha->drq);
4725		- shp->unchecked_isa_dma = 1;
4726		- shp->irq = ha->irq;
4727		- shp->dma_channel = ha->drq;
4728		-
4729		- ha->hanum = gdth_ctr_count++;
4730		- ha->shost = shp;
4731		-
4732		- ha->pccb = &ha->cmdext;
4733		- ha->ccb_phys = 0L;
4734		- ha->pdev = NULL;
4735		-
4736		- error = -ENOMEM;
4737		-
4738		- ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4739		- &scratch_dma_handle);
4740		- if (!ha->pscratch)
4741		- goto out_dec_counters;
4742		- ha->scratch_phys = scratch_dma_handle;
4743		-
4744		- ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4745		- &scratch_dma_handle);
4746		- if (!ha->pmsg)
4747		- goto out_free_pscratch;
4748		- ha->msg_phys = scratch_dma_handle;
4749		-
4750		-#ifdef INT_COAL
4751		- ha->coal_stat = pci_alloc_consistent(ha->pdev,
4752		- sizeof(gdth_coal_status) * MAXOFFSETS,
4753		- &scratch_dma_handle);
4754		- if (!ha->coal_stat)
4755		- goto out_free_pmsg;
4756		- ha->coal_stat_phys = scratch_dma_handle;
4757		-#endif
4758		-
4759		- ha->scratch_busy = FALSE;
4760		- ha->req_first = NULL;
4761		- ha->tid_cnt = MAX_HDRIVES;
4762		- if (max_ids > 0 && max_ids < ha->tid_cnt)
4763		- ha->tid_cnt = max_ids;
4764		- for (i = 0; i < GDTH_MAXCMDS; ++i)
4765		- ha->cmd_tab[i].cmnd = UNUSED_CMND;
4766		- ha->scan_mode = rescan ? 0x10 : 0;
4767		-
4768		- error = -ENODEV;
4769		- if (!gdth_search_drives(ha)) {
4770		- printk("GDT-ISA: Error during device scan\n");
4771		- goto out_free_coal_stat;
4772		- }
4773		-
4774		- if (hdr_channel < 0 \|\| hdr_channel > ha->bus_cnt)
4775		- hdr_channel = ha->bus_cnt;
4776		- ha->virt_bus = hdr_channel;
4777		-
4778		- if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4779		- shp->max_cmd_len = 16;
4780		-
4781		- shp->max_id = ha->tid_cnt;
4782		- shp->max_lun = MAXLUN;
4783		- shp->max_channel = ha->bus_cnt;
4784		-
4785		- spin_lock_init(&ha->smp_lock);
4786		- gdth_enable_int(ha);
4787		-
4788		- error = scsi_add_host(shp, NULL);
4789		- if (error)
4790		- goto out_free_coal_stat;
4791		- list_add_tail(&ha->list, &gdth_instances);
4792		- gdth_timer_init();
4793		-
4794		- scsi_scan_host(shp);
4795		-
4796		- return 0;
4797		-
4798		- out_free_coal_stat:
4799		-#ifdef INT_COAL
4800		- pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4801		- ha->coal_stat, ha->coal_stat_phys);
4802		- out_free_pmsg:
4803		-#endif
4804		- pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4805		- ha->pmsg, ha->msg_phys);
4806		- out_free_pscratch:
4807		- pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4808		- ha->pscratch, ha->scratch_phys);
4809		- out_dec_counters:
4810		- gdth_ctr_count--;
4811		- out_free_irq:
4812		- free_irq(ha->irq, ha);
4813		- out_host_put:
4814		- scsi_host_put(shp);
4815		- return error;
4816		-}
4817		-#endif /* CONFIG_ISA */
4818		-
4819		-#ifdef CONFIG_EISA
4820		-static int __init gdth_eisa_probe_one(u16 eisa_slot)
4821		-{
4822		- struct Scsi_Host *shp;
4823		- gdth_ha_str *ha;
4824		- dma_addr_t scratch_dma_handle = 0;
4825		- int error, i;
4826		-
4827		- if (!gdth_search_eisa(eisa_slot))
4828		- return -ENXIO;
4829		-
4830		- shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4831		- if (!shp)
4832		- return -ENOMEM;
4833		- ha = shost_priv(shp);
4834		-
4835		- error = -ENODEV;
4836		- if (!gdth_init_eisa(eisa_slot,ha))
4837		- goto out_host_put;
4838		-
4839		- /* controller found and initialized */
4840		- printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4841		- eisa_slot >> 12, ha->irq);
4842		-
4843		- error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
4844		- if (error) {
4845		- printk("GDT-EISA: Unable to allocate IRQ\n");
4846		- goto out_host_put;
4847		- }
4848		-
4849		- shp->unchecked_isa_dma = 0;
4850		- shp->irq = ha->irq;
4851		- shp->dma_channel = 0xff;
4852		-
4853		- ha->hanum = gdth_ctr_count++;
4854		- ha->shost = shp;
4855		-
4856		- TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
4857		-
4858		- ha->pccb = &ha->cmdext;
4859		- ha->ccb_phys = 0L;
4860		-
4861		- error = -ENOMEM;
4862		-
4863		- ha->pdev = NULL;
4864		- ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4865		- &scratch_dma_handle);
4866		- if (!ha->pscratch)
4867		- goto out_free_irq;
4868		- ha->scratch_phys = scratch_dma_handle;
4869		-
4870		- ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4871		- &scratch_dma_handle);
4872		- if (!ha->pmsg)
4873		- goto out_free_pscratch;
4874		- ha->msg_phys = scratch_dma_handle;
4875		-
4876		-#ifdef INT_COAL
4877		- ha->coal_stat = pci_alloc_consistent(ha->pdev,
4878		- sizeof(gdth_coal_status) * MAXOFFSETS,
4879		- &scratch_dma_handle);
4880		- if (!ha->coal_stat)
4881		- goto out_free_pmsg;
4882		- ha->coal_stat_phys = scratch_dma_handle;
4883		-#endif
4884		-
4885		- ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
4886		- sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
4887		- if (!ha->ccb_phys)
4888		- goto out_free_coal_stat;
4889		-
4890		- ha->scratch_busy = FALSE;
4891		- ha->req_first = NULL;
4892		- ha->tid_cnt = MAX_HDRIVES;
4893		- if (max_ids > 0 && max_ids < ha->tid_cnt)
4894		- ha->tid_cnt = max_ids;
4895		- for (i = 0; i < GDTH_MAXCMDS; ++i)
4896		- ha->cmd_tab[i].cmnd = UNUSED_CMND;
4897		- ha->scan_mode = rescan ? 0x10 : 0;
4898		-
4899		- if (!gdth_search_drives(ha)) {
4900		- printk("GDT-EISA: Error during device scan\n");
4901		- error = -ENODEV;
4902		- goto out_free_ccb_phys;
4903		- }
4904		-
4905		- if (hdr_channel < 0 \|\| hdr_channel > ha->bus_cnt)
4906		- hdr_channel = ha->bus_cnt;
4907		- ha->virt_bus = hdr_channel;
4908		-
4909		- if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4910		- shp->max_cmd_len = 16;
4911		-
4912		- shp->max_id = ha->tid_cnt;
4913		- shp->max_lun = MAXLUN;
4914		- shp->max_channel = ha->bus_cnt;
4915		-
4916		- spin_lock_init(&ha->smp_lock);
4917		- gdth_enable_int(ha);
4918		-
4919		- error = scsi_add_host(shp, NULL);
4920		- if (error)
4921		- goto out_free_ccb_phys;
4922		- list_add_tail(&ha->list, &gdth_instances);
4923		- gdth_timer_init();
4924		-
4925		- scsi_scan_host(shp);
4926		-
4927		- return 0;
4928		-
4929		- out_free_ccb_phys:
4930		- pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
4931		- PCI_DMA_BIDIRECTIONAL);
4932		- out_free_coal_stat:
4933		-#ifdef INT_COAL
4934		- pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4935		- ha->coal_stat, ha->coal_stat_phys);
4936		- out_free_pmsg:
4937		-#endif
4938		- pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4939		- ha->pmsg, ha->msg_phys);
4940		- out_free_pscratch:
4941		- pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4942		- ha->pscratch, ha->scratch_phys);
4943		- out_free_irq:
4944		- free_irq(ha->irq, ha);
4945		- gdth_ctr_count--;
4946		- out_host_put:
4947		- scsi_host_put(shp);
4948		- return error;
4949		-}
4950		-#endif /* CONFIG_EISA */
4951		-
4952		-#ifdef CONFIG_PCI
4953	4013	static int gdth_pci_probe_one(gdth_pci_str pcistr, gdth_ha_str *ha_out)
4954	4014	{
4955	4015	struct Scsi_Host *shp;
..	..	@@ -4994,26 +4054,17 @@
4994	4054
4995	4055	error = -ENOMEM;
4996	4056
4997		- ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4998		- &scratch_dma_handle);
	4057	+ ha->pscratch = dma_alloc_coherent(&ha->pdev->dev, GDTH_SCRATCH,
	4058	+ &scratch_dma_handle, GFP_KERNEL);
4999	4059	if (!ha->pscratch)
5000	4060	goto out_free_irq;
5001	4061	ha->scratch_phys = scratch_dma_handle;
5002	4062
5003		- ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5004		- &scratch_dma_handle);
	4063	+ ha->pmsg = dma_alloc_coherent(&ha->pdev->dev, sizeof(gdth_msg_str),
	4064	+ &scratch_dma_handle, GFP_KERNEL);
5005	4065	if (!ha->pmsg)
5006	4066	goto out_free_pscratch;
5007	4067	ha->msg_phys = scratch_dma_handle;
5008		-
5009		-#ifdef INT_COAL
5010		- ha->coal_stat = pci_alloc_consistent(ha->pdev,
5011		- sizeof(gdth_coal_status) * MAXOFFSETS,
5012		- &scratch_dma_handle);
5013		- if (!ha->coal_stat)
5014		- goto out_free_pmsg;
5015		- ha->coal_stat_phys = scratch_dma_handle;
5016		-#endif
5017	4068
5018	4069	ha->scratch_busy = FALSE;
5019	4070	ha->req_first = NULL;
..	..	@@ -5027,7 +4078,7 @@
5027	4078	error = -ENODEV;
5028	4079	if (!gdth_search_drives(ha)) {
5029	4080	printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
5030		- goto out_free_coal_stat;
	4081	+ goto out_free_pmsg;
5031	4082	}
5032	4083
5033	4084	if (hdr_channel < 0 \|\| hdr_channel > ha->bus_cnt)
..	..	@@ -5037,19 +4088,19 @@
5037	4088	/* 64-bit DMA only supported from FW >= x.43 */
5038	4089	if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) \|\|
5039	4090	!ha->dma64_support) {
5040		- if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
	4091	+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
5041	4092	printk(KERN_WARNING "GDT-PCI %d: "
5042	4093	"Unable to set 32-bit DMA\n", ha->hanum);
5043		- goto out_free_coal_stat;
	4094	+ goto out_free_pmsg;
5044	4095	}
5045	4096	} else {
5046	4097	shp->max_cmd_len = 16;
5047		- if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
	4098	+ if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
5048	4099	printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
5049		- } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
	4100	+ } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
5050	4101	printk(KERN_WARNING "GDT-PCI %d: "
5051	4102	"Unable to set 64/32-bit DMA\n", ha->hanum);
5052		- goto out_free_coal_stat;
	4103	+ goto out_free_pmsg;
5053	4104	}
5054	4105	}
5055	4106
..	..	@@ -5062,7 +4113,7 @@
5062	4113
5063	4114	error = scsi_add_host(shp, &pdev->dev);
5064	4115	if (error)
5065		- goto out_free_coal_stat;
	4116	+ goto out_free_pmsg;
5066	4117	list_add_tail(&ha->list, &gdth_instances);
5067	4118
5068	4119	pci_set_drvdata(ha->pdev, ha);
..	..	@@ -5074,16 +4125,11 @@
5074	4125
5075	4126	return 0;
5076	4127
5077		- out_free_coal_stat:
5078		-#ifdef INT_COAL
5079		- pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5080		- ha->coal_stat, ha->coal_stat_phys);
5081	4128	out_free_pmsg:
5082		-#endif
5083		- pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
	4129	+ dma_free_coherent(&ha->pdev->dev, sizeof(gdth_msg_str),
5084	4130	ha->pmsg, ha->msg_phys);
5085	4131	out_free_pscratch:
5086		- pci_free_consistent(ha->pdev, GDTH_SCRATCH,
	4132	+ dma_free_coherent(&ha->pdev->dev, GDTH_SCRATCH,
5087	4133	ha->pscratch, ha->scratch_phys);
5088	4134	out_free_irq:
5089	4135	free_irq(ha->irq, ha);
..	..	@@ -5092,7 +4138,6 @@
5092	4138	scsi_host_put(shp);
5093	4139	return error;
5094	4140	}
5095		-#endif /* CONFIG_PCI */
5096	4141
5097	4142	static void gdth_remove_one(gdth_ha_str *ha)
5098	4143	{
..	..	@@ -5112,24 +4157,15 @@
5112	4157	if (shp->irq)
5113	4158	free_irq(shp->irq,ha);
5114	4159
5115		-#ifdef CONFIG_ISA
5116		- if (shp->dma_channel != 0xff)
5117		- free_dma(shp->dma_channel);
5118		-#endif
5119		-#ifdef INT_COAL
5120		- if (ha->coal_stat)
5121		- pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5122		- MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5123		-#endif
5124	4160	if (ha->pscratch)
5125		- pci_free_consistent(ha->pdev, GDTH_SCRATCH,
	4161	+ dma_free_coherent(&ha->pdev->dev, GDTH_SCRATCH,
5126	4162	ha->pscratch, ha->scratch_phys);
5127	4163	if (ha->pmsg)
5128		- pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
	4164	+ dma_free_coherent(&ha->pdev->dev, sizeof(gdth_msg_str),
5129	4165	ha->pmsg, ha->msg_phys);
5130	4166	if (ha->ccb_phys)
5131		- pci_unmap_single(ha->pdev,ha->ccb_phys,
5132		- sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
	4167	+ dma_unmap_single(&ha->pdev->dev, ha->ccb_phys,
	4168	+ sizeof(gdth_cmd_str), DMA_BIDIRECTIONAL);
5133	4169
5134	4170	scsi_host_put(shp);
5135	4171	}
..	..	@@ -5168,26 +4204,6 @@
5168	4204	gdth_clear_events();
5169	4205	timer_setup(&gdth_timer, gdth_timeout, 0);
5170	4206
5171		- /* As default we do not probe for EISA or ISA controllers */
5172		- if (probe_eisa_isa) {
5173		- /* scanning for controllers, at first: ISA controller */
5174		-#ifdef CONFIG_ISA
5175		- u32 isa_bios;
5176		- for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
5177		- isa_bios += 0x8000UL)
5178		- gdth_isa_probe_one(isa_bios);
5179		-#endif
5180		-#ifdef CONFIG_EISA
5181		- {
5182		- u16 eisa_slot;
5183		- for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
5184		- eisa_slot += 0x1000)
5185		- gdth_eisa_probe_one(eisa_slot);
5186		- }
5187		-#endif
5188		- }
5189		-
5190		-#ifdef CONFIG_PCI
5191	4207	/* scanning for PCI controllers */
5192	4208	if (pci_register_driver(&gdth_pci_driver)) {
5193	4209	gdth_ha_str *ha;
..	..	@@ -5196,7 +4212,6 @@
5196	4212	gdth_remove_one(ha);
5197	4213	return -ENODEV;
5198	4214	}
5199		-#endif /* CONFIG_PCI */
5200	4215
5201	4216	TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5202	4217
..	..	@@ -5217,9 +4232,7 @@
5217	4232	del_timer_sync(&gdth_timer);
5218	4233	#endif
5219	4234
5220		-#ifdef CONFIG_PCI
5221	4235	pci_unregister_driver(&gdth_pci_driver);
5222		-#endif
5223	4236
5224	4237	list_for_each_entry(ha, &gdth_instances, list)
5225	4238	gdth_remove_one(ha);
..	..	@@ -5229,5 +4242,81 @@
5229	4242	module_exit(gdth_exit);
5230	4243
5231	4244	#ifndef MODULE
	4245	+static void __init internal_setup(char str,int ints)
	4246	+{
	4247	+ int i;
	4248	+ char cur_str, argv;
	4249	+
	4250	+ TRACE2(("internal_setup() str %s ints[0] %d\n",
	4251	+ str ? str:"NULL", ints ? ints[0]:0));
	4252	+
	4253	+ /* analyse string */
	4254	+ argv = str;
	4255	+ while (argv && (cur_str = strchr(argv, ':'))) {
	4256	+ int val = 0, c = *++cur_str;
	4257	+
	4258	+ if (c == 'n' \|\| c == 'N')
	4259	+ val = 0;
	4260	+ else if (c == 'y' \|\| c == 'Y')
	4261	+ val = 1;
	4262	+ else
	4263	+ val = (int)simple_strtoul(cur_str, NULL, 0);
	4264	+
	4265	+ if (!strncmp(argv, "disable:", 8))
	4266	+ disable = val;
	4267	+ else if (!strncmp(argv, "reserve_mode:", 13))
	4268	+ reserve_mode = val;
	4269	+ else if (!strncmp(argv, "reverse_scan:", 13))
	4270	+ reverse_scan = val;
	4271	+ else if (!strncmp(argv, "hdr_channel:", 12))
	4272	+ hdr_channel = val;
	4273	+ else if (!strncmp(argv, "max_ids:", 8))
	4274	+ max_ids = val;
	4275	+ else if (!strncmp(argv, "rescan:", 7))
	4276	+ rescan = val;
	4277	+ else if (!strncmp(argv, "shared_access:", 14))
	4278	+ shared_access = val;
	4279	+ else if (!strncmp(argv, "reserve_list:", 13)) {
	4280	+ reserve_list[0] = val;
	4281	+ for (i = 1; i < MAX_RES_ARGS; i++) {
	4282	+ cur_str = strchr(cur_str, ',');
	4283	+ if (!cur_str)
	4284	+ break;
	4285	+ if (!isdigit((int)*++cur_str)) {
	4286	+ --cur_str;
	4287	+ break;
	4288	+ }
	4289	+ reserve_list[i] =
	4290	+ (int)simple_strtoul(cur_str, NULL, 0);
	4291	+ }
	4292	+ if (!cur_str)
	4293	+ break;
	4294	+ argv = ++cur_str;
	4295	+ continue;
	4296	+ }
	4297	+
	4298	+ if ((argv = strchr(argv, ',')))
	4299	+ ++argv;
	4300	+ }
	4301	+}
	4302	+
	4303	+static int __init option_setup(char *str)
	4304	+{
	4305	+ int ints[MAXHA];
	4306	+ char *cur = str;
	4307	+ int i = 1;
	4308	+
	4309	+ TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
	4310	+
	4311	+ while (cur && isdigit(*cur) && i < MAXHA) {
	4312	+ ints[i++] = simple_strtoul(cur, NULL, 0);
	4313	+ if ((cur = strchr(cur, ',')) != NULL) cur++;
	4314	+ }
	4315	+
	4316	+ ints[0] = i - 1;
	4317	+ internal_setup(cur, ints);
	4318	+ return 1;
	4319	+}
	4320	+
5232	4321	__setup("gdth=", option_setup);
5233	4322	#endif