| .. | .. |
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| 78 | 78 | #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ |
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| 79 | 79 | #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ |
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| 80 | 80 | |
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| 81 | | -/* ESP config register 4 read-write, found only on am53c974 chips */ |
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| 82 | | -#define ESP_CONFIG4_RADE 0x04 /* Active negation */ |
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| 83 | | -#define ESP_CONFIG4_RAE 0x08 /* Active negation on REQ and ACK */ |
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| 84 | | -#define ESP_CONFIG4_PWD 0x20 /* Reduced power feature */ |
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| 85 | | -#define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 */ |
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| 86 | | -#define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 */ |
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| 81 | +/* ESP config register 4 read-write */ |
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| 82 | +#define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */ |
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| 83 | +#define ESP_CONGIG4_TEST 0x02 /* Transfer counter test mode (fsc) */ |
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| 84 | +#define ESP_CONFIG4_RADE 0x04 /* Active negation (am53c974/fsc) */ |
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| 85 | +#define ESP_CONFIG4_RAE 0x08 /* Act. negation REQ/ACK (am53c974) */ |
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| 86 | +#define ESP_CONFIG4_PWD 0x20 /* Reduced power feature (am53c974) */ |
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| 87 | +#define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 (am53c974) */ |
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| 88 | +#define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 (am53c974) */ |
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| 87 | 89 | |
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| 88 | 90 | #define ESP_CONFIG_GE_12NS (0) |
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| 89 | 91 | #define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1) |
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| .. | .. |
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| 209 | 211 | #define ESP_TEST_TS 0x04 /* Tristate test mode */ |
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| 210 | 212 | |
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| 211 | 213 | /* ESP unique ID register read-only, found on fas236+fas100a only */ |
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| 214 | +#define ESP_UID_FAM 0xf8 /* ESP family bitmask */ |
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| 215 | + |
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| 216 | +#define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3) |
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| 217 | + |
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| 218 | +/* Values for the ESP family bits */ |
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| 212 | 219 | #define ESP_UID_F100A 0x00 /* ESP FAS100A */ |
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| 213 | 220 | #define ESP_UID_F236 0x02 /* ESP FAS236 */ |
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| 214 | | -#define ESP_UID_REV 0x07 /* ESP revision */ |
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| 215 | | -#define ESP_UID_FAM 0xf8 /* ESP family */ |
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| 221 | +#define ESP_UID_HME 0x0a /* FAS HME */ |
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| 222 | +#define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */ |
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| 216 | 223 | |
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| 217 | 224 | /* ESP fifo flags register read-only */ |
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| 218 | 225 | /* Note that the following implies a 16 byte FIFO on the ESP. */ |
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| .. | .. |
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| 249 | 256 | #define SYNC_DEFP_FAST 0x19 /* 10mb/s */ |
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| 250 | 257 | |
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| 251 | 258 | struct esp_cmd_priv { |
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| 252 | | - union { |
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| 253 | | - dma_addr_t dma_addr; |
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| 254 | | - int num_sg; |
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| 255 | | - } u; |
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| 256 | | - |
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| 259 | + int num_sg; |
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| 257 | 260 | int cur_residue; |
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| 261 | + struct scatterlist *prv_sg; |
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| 258 | 262 | struct scatterlist *cur_sg; |
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| 259 | 263 | int tot_residue; |
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| 260 | 264 | }; |
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| 261 | 265 | #define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp)) |
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| 262 | 266 | |
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| 267 | +/* NOTE: this enum is ordered based on chip features! */ |
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| 263 | 268 | enum esp_rev { |
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| 264 | | - ESP100 = 0x00, /* NCR53C90 - very broken */ |
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| 265 | | - ESP100A = 0x01, /* NCR53C90A */ |
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| 266 | | - ESP236 = 0x02, |
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| 267 | | - FAS236 = 0x03, |
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| 268 | | - FAS100A = 0x04, |
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| 269 | | - FAST = 0x05, |
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| 270 | | - FASHME = 0x06, |
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| 271 | | - PCSCSI = 0x07, /* AM53c974 */ |
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| 269 | + ESP100, /* NCR53C90 - very broken */ |
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| 270 | + ESP100A, /* NCR53C90A */ |
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| 271 | + ESP236, |
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| 272 | + FAS236, |
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| 273 | + PCSCSI, /* AM53c974 */ |
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| 274 | + FSC, /* NCR/Symbios Logic 53CF9x-2 */ |
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| 275 | + FAS100A, |
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| 276 | + FAST, |
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| 277 | + FASHME, |
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| 272 | 278 | }; |
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| 273 | 279 | |
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| 274 | 280 | struct esp_cmd_entry { |
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| .. | .. |
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| 277 | 283 | struct scsi_cmnd *cmd; |
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| 278 | 284 | |
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| 279 | 285 | unsigned int saved_cur_residue; |
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| 286 | + struct scatterlist *saved_prv_sg; |
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| 280 | 287 | struct scatterlist *saved_cur_sg; |
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| 281 | 288 | unsigned int saved_tot_residue; |
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| 282 | 289 | |
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| .. | .. |
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| 363 | 370 | void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg); |
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| 364 | 371 | u8 (*esp_read8)(struct esp *esp, unsigned long reg); |
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| 365 | 372 | |
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| 366 | | - /* Map and unmap DMA memory. Eventually the driver will be |
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| 367 | | - * converted to the generic DMA API as soon as SBUS is able to |
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| 368 | | - * cope with that. At such time we can remove this. |
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| 369 | | - */ |
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| 370 | | - dma_addr_t (*map_single)(struct esp *esp, void *buf, |
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| 371 | | - size_t sz, int dir); |
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| 372 | | - int (*map_sg)(struct esp *esp, struct scatterlist *sg, |
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| 373 | | - int num_sg, int dir); |
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| 374 | | - void (*unmap_single)(struct esp *esp, dma_addr_t addr, |
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| 375 | | - size_t sz, int dir); |
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| 376 | | - void (*unmap_sg)(struct esp *esp, struct scatterlist *sg, |
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| 377 | | - int num_sg, int dir); |
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| 378 | | - |
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| 379 | 373 | /* Return non-zero if there is an IRQ pending. Usually this |
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| 380 | 374 | * status bit lives in the DMA controller sitting in front of |
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| 381 | 375 | * the ESP. This has to be accurate or else the ESP interrupt |
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| .. | .. |
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| 435 | 429 | const struct esp_driver_ops *ops; |
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| 436 | 430 | |
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| 437 | 431 | struct Scsi_Host *host; |
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| 438 | | - void *dev; |
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| 432 | + struct device *dev; |
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| 439 | 433 | |
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| 440 | 434 | struct esp_cmd_entry *active_cmd; |
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| 441 | 435 | |
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| .. | .. |
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| 490 | 484 | u32 flags; |
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| 491 | 485 | #define ESP_FLAG_DIFFERENTIAL 0x00000001 |
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| 492 | 486 | #define ESP_FLAG_RESETTING 0x00000002 |
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| 493 | | -#define ESP_FLAG_DOING_SLOWCMD 0x00000004 |
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| 494 | 487 | #define ESP_FLAG_WIDE_CAPABLE 0x00000008 |
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| 495 | 488 | #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010 |
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| 496 | 489 | #define ESP_FLAG_DISABLE_SYNC 0x00000020 |
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| 497 | 490 | #define ESP_FLAG_USE_FIFO 0x00000040 |
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| 491 | +#define ESP_FLAG_NO_DMA_MAP 0x00000080 |
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| 498 | 492 | |
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| 499 | 493 | u8 select_state; |
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| 500 | 494 | #define ESP_SELECT_NONE 0x00 /* Not selecting */ |
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| .. | .. |
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| 532 | 526 | u32 min_period; |
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| 533 | 527 | u32 radelay; |
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| 534 | 528 | |
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| 535 | | - /* Slow command state. */ |
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| 529 | + /* ESP_CMD_SELAS command state */ |
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| 536 | 530 | u8 *cmd_bytes_ptr; |
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| 537 | 531 | int cmd_bytes_left; |
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| 538 | 532 | |
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| .. | .. |
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| 541 | 535 | void *dma; |
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| 542 | 536 | int dmarev; |
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| 543 | 537 | |
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| 538 | + /* These are used by esp_send_pio_cmd() */ |
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| 539 | + u8 __iomem *fifo_reg; |
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| 540 | + int send_cmd_error; |
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| 544 | 541 | u32 send_cmd_residual; |
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| 545 | 542 | }; |
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| 546 | 543 | |
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| .. | .. |
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| 570 | 567 | * example, the DMA engine has to be reset before ESP can |
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| 571 | 568 | * be programmed. |
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| 572 | 569 | * 11) If necessary, call dev_set_drvdata() as needed. |
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| 573 | | - * 12) Call scsi_esp_register() with prepared 'esp' structure |
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| 574 | | - * and a device pointer if possible. |
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| 570 | + * 12) Call scsi_esp_register() with prepared 'esp' structure. |
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| 575 | 571 | * 13) Check scsi_esp_register() return value, release all resources |
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| 576 | 572 | * if an error was returned. |
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| 577 | 573 | */ |
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| 578 | 574 | extern struct scsi_host_template scsi_esp_template; |
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| 579 | | -extern int scsi_esp_register(struct esp *, struct device *); |
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| 575 | +extern int scsi_esp_register(struct esp *); |
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| 580 | 576 | |
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| 581 | 577 | extern void scsi_esp_unregister(struct esp *); |
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| 582 | 578 | extern irqreturn_t scsi_esp_intr(int, void *); |
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| 583 | 579 | extern void scsi_esp_cmd(struct esp *, u8); |
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| 584 | 580 | |
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| 581 | +extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count, |
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| 582 | + u32 dma_count, int write, u8 cmd); |
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| 583 | + |
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| 585 | 584 | #endif /* !(_ESP_SCSI_H) */ |
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