| .. | .. |
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| 629 | 629 | return 0; |
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| 630 | 630 | } |
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| 631 | 631 | |
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| 632 | | -static struct regulator_ops ti_abb_reg_ops = { |
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| 632 | +static const struct regulator_ops ti_abb_reg_ops = { |
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| 633 | 633 | .list_voltage = regulator_list_voltage_table, |
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| 634 | 634 | |
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| 635 | 635 | .set_voltage_sel = ti_abb_set_voltage_sel, |
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| .. | .. |
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| 758 | 758 | * We may have shared interrupt register offsets which are |
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| 759 | 759 | * write-1-to-clear between domains ensuring exclusivity. |
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| 760 | 760 | */ |
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| 761 | | - abb->int_base = devm_ioremap_nocache(dev, res->start, |
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| 761 | + abb->int_base = devm_ioremap(dev, res->start, |
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| 762 | 762 | resource_size(res)); |
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| 763 | 763 | if (!abb->int_base) { |
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| 764 | 764 | dev_err(dev, "Unable to map '%s'\n", pname); |
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| .. | .. |
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| 778 | 778 | * We may have shared efuse register offsets which are read-only |
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| 779 | 779 | * between domains |
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| 780 | 780 | */ |
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| 781 | | - abb->efuse_base = devm_ioremap_nocache(dev, res->start, |
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| 781 | + abb->efuse_base = devm_ioremap(dev, res->start, |
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| 782 | 782 | resource_size(res)); |
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| 783 | 783 | if (!abb->efuse_base) { |
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| 784 | 784 | dev_err(dev, "Unable to map '%s'\n", pname); |
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