forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/regulator/cpcap-regulator.c
....@@ -89,8 +89,8 @@
8989  */
9090 #define CPCAP_REG_OFF_MODE_SEC		BIT(15)
9191 
92
-/**
93
- * SoC specific configuraion for CPCAP regulator. There are at least three
92
+/*
93
+ * SoC specific configuration for CPCAP regulator. There are at least three
9494  * different SoCs each with their own parameters: omap3, omap4 and tegra2.
9595  *
9696  * The assign_reg and assign_mask seem to allow toggling between primary
....@@ -100,12 +100,11 @@
100100 	struct regulator_desc rdesc;
101101 	const u16 assign_reg;
102102 	const u16 assign_mask;
103
-	const u16 vsel_shift;
104103 };
105104 
106105 #define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl,	\
107
-		mode_mask, volt_mask, volt_shft,			\
108
-		mode_val, off_val, volt_trans_time) {			\
106
+		mode_mask, volt_mask, mode_val, off_val,		\
107
+		volt_trans_time) {					\
109108 	.rdesc = {							\
110109 		.name = #_ID,						\
111110 		.of_match = of_match_ptr(#_ID),				\
....@@ -127,7 +126,6 @@
127126 	},								\
128127 	.assign_reg = (assignment_reg),					\
129128 	.assign_mask = (assignment_mask),				\
130
-	.vsel_shift = (volt_shft),					\
131129 }
132130 
133131 struct cpcap_ddata {
....@@ -171,7 +169,7 @@
171169 static int cpcap_regulator_enable(struct regulator_dev *rdev)
172170 {
173171 	struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
174
-	int error, ignore;
172
+	int error;
175173 
176174 	error = regulator_enable_regmap(rdev);
177175 	if (error)
....@@ -182,7 +180,7 @@
182180 					   regulator->assign_mask,
183181 					   regulator->assign_mask);
184182 		if (error)
185
-			ignore = regulator_disable_regmap(rdev);
183
+			regulator_disable_regmap(rdev);
186184 	}
187185 
188186 	return error;
....@@ -195,7 +193,7 @@
195193 static int cpcap_regulator_disable(struct regulator_dev *rdev)
196194 {
197195 	struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
198
-	int error, ignore;
196
+	int error;
199197 
200198 	if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
201199 		error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
....@@ -206,9 +204,9 @@
206204 
207205 	error = regulator_disable_regmap(rdev);
208206 	if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
209
-		ignore = regmap_update_bits(rdev->regmap, regulator->assign_reg,
210
-					    regulator->assign_mask,
211
-					    regulator->assign_mask);
207
+		regmap_update_bits(rdev->regmap, regulator->assign_reg,
208
+				   regulator->assign_mask,
209
+				   regulator->assign_mask);
212210 	}
213211 
214212 	return error;
....@@ -258,7 +256,7 @@
258256 				  CPCAP_BIT_AUDIO_LOW_PWR, value);
259257 }
260258 
261
-static struct regulator_ops cpcap_regulator_ops = {
259
+static const struct regulator_ops cpcap_regulator_ops = {
262260 	.enable = cpcap_regulator_enable,
263261 	.disable = cpcap_regulator_disable,
264262 	.is_enabled = regulator_is_enabled_regmap,
....@@ -327,7 +325,7 @@
327325 static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
328326 static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };
329327 
330
-/**
328
+/*
331329  * SoC specific configuration for omap4. The data below is comes from Motorola
332330  * Linux kernel tree. It's basically the values of cpcap_regltr_data,
333331  * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
....@@ -336,155 +334,155 @@
336334  * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
337335  * VSIMCARD have a shared resource assignment bit.
338336  */
339
-static struct cpcap_regulator omap4_regulators[] = {
337
+static const struct cpcap_regulator omap4_regulators[] = {
340338 	CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
341339 		  CPCAP_BIT_SW1_SEL, unknown_val_tbl,
342
-		  0, 0, 0, 0, 0, 0),
340
+		  0, 0, 0, 0, 0),
343341 	CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
344342 		  CPCAP_BIT_SW2_SEL, unknown_val_tbl,
345
-		  0, 0, 0, 0, 0, 0),
343
+		  0, 0, 0, 0, 0),
346344 	CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
347345 		  CPCAP_BIT_SW3_SEL, unknown_val_tbl,
348
-		  0, 0, 0, 0, 0, 0),
346
+		  0, 0, 0, 0, 0),
349347 	CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
350348 		  CPCAP_BIT_SW4_SEL, unknown_val_tbl,
351
-		  0, 0, 0, 0, 0, 0),
349
+		  0, 0, 0, 0, 0),
352350 	CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
353351 		  CPCAP_BIT_SW5_SEL, sw5_val_tbl,
354
-		  0x28, 0, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
352
+		  0x28, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
355353 	CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
356354 		  CPCAP_BIT_SW6_SEL, unknown_val_tbl,
357
-		  0, 0, 0, 0, 0, 0),
355
+		  0, 0, 0, 0, 0),
358356 	CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
359357 		  CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
360
-		  0x87, 0x30, 4, 0x3, 0, 420),
358
+		  0x87, 0x30, 0x3, 0, 420),
361359 	CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
362360 		  CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
363
-		  0x47, 0x10, 4, 0x43, 0x41, 350),
361
+		  0x47, 0x10, 0x43, 0x41, 350),
364362 	CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
365363 		  CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
366
-		  0x87, 0x30, 4, 0x3, 0, 420),
364
+		  0x87, 0x30, 0x3, 0, 420),
367365 	CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
368366 		  CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
369
-		  0x87, 0x30, 4, 0x82, 0, 420),
367
+		  0x87, 0x30, 0x82, 0, 420),
370368 	CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
371369 		  CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
372
-		  0x80, 0xf, 0, 0x80, 0, 420),
370
+		  0x80, 0xf, 0x80, 0, 420),
373371 	CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
374372 		  CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
375
-		  0x17, 0, 0, 0, 0x12, 0),
373
+		  0x17, 0, 0, 0x12, 0),
376374 	CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
377375 		  CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
378
-		  0x87, 0x38, 3, 0x82, 0, 420),
376
+		  0x87, 0x38, 0x82, 0, 420),
379377 	CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
380378 		  CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
381
-		  0x43, 0x18, 3, 0x2, 0, 420),
379
+		  0x43, 0x18, 0x2, 0, 420),
382380 	CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
383381 		  CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
384
-		  0xac, 0x2, 1, 0x4, 0, 10),
382
+		  0xac, 0x2, 0x4, 0, 10),
385383 	CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
386384 		  CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
387
-		  0x23, 0x8, 3, 0, 0, 10),
385
+		  0x23, 0x8, 0, 0, 10),
388386 	CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
389387 		  CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
390
-		  0x23, 0x8, 3, 0, 0, 420),
388
+		  0x23, 0x8, 0, 0, 420),
391389 	CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
392390 		  CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
393
-		  0x47, 0x10, 4, 0, 0, 420),
391
+		  0x47, 0x10, 0, 0, 420),
394392 	CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
395393 		  CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
396
-		  0x20c, 0xc0, 6, 0x20c, 0, 420),
394
+		  0x20c, 0xc0, 0x20c, 0, 420),
397395 	CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
398396 		  0xffff, vsim_val_tbl,
399
-		  0x23, 0x8, 3, 0x3, 0, 420),
397
+		  0x23, 0x8, 0x3, 0, 420),
400398 	CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
401399 		  0xffff, vsimcard_val_tbl,
402
-		  0x1e80, 0x8, 3, 0x1e00, 0, 420),
400
+		  0x1e80, 0x8, 0x1e00, 0, 420),
403401 	CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
404402 		  CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
405
-		  0x1, 0xc, 2, 0x1, 0, 500),
403
+		  0x1, 0xc, 0x1, 0, 500),
406404 	CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
407405 		  CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
408
-		  0x11c, 0x40, 6, 0xc, 0, 0),
406
+		  0x11c, 0x40, 0xc, 0, 0),
409407 	CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
410408 		  CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
411
-		  0x16, 0x1, 0, 0x4, 0, 0),
409
+		  0x16, 0x1, 0x4, 0, 0),
412410 	{ /* sentinel */ },
413411 };
414412 
415
-static struct cpcap_regulator xoom_regulators[] = {
413
+static const struct cpcap_regulator xoom_regulators[] = {
416414 	CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
417415 		  CPCAP_BIT_SW1_SEL, unknown_val_tbl,
418
-		  0, 0, 0, 0, 0, 0),
416
+		  0, 0, 0, 0, 0),
419417 	CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
420418 		  CPCAP_BIT_SW2_SEL, sw2_sw4_val_tbl,
421
-		  0xf00, 0x7f, 0, 0x800, 0, 120),
419
+		  0xf00, 0x7f, 0x800, 0, 120),
422420 	CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
423421 		  CPCAP_BIT_SW3_SEL, unknown_val_tbl,
424
-		  0, 0, 0, 0, 0, 0),
422
+		  0, 0, 0, 0, 0),
425423 	CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
426424 		  CPCAP_BIT_SW4_SEL, sw2_sw4_val_tbl,
427
-		  0xf00, 0x7f, 0, 0x900, 0, 100),
425
+		  0xf00, 0x7f, 0x900, 0, 100),
428426 	CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
429427 		  CPCAP_BIT_SW5_SEL, sw5_val_tbl,
430
-		  0x2a, 0, 0, 0x22, 0, 0),
428
+		  0x2a, 0, 0x22, 0, 0),
431429 	CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
432430 		  CPCAP_BIT_SW6_SEL, unknown_val_tbl,
433
-		  0, 0, 0, 0, 0, 0),
431
+		  0, 0, 0, 0, 0),
434432 	CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
435433 		  CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
436
-		  0x87, 0x30, 4, 0x7, 0, 420),
434
+		  0x87, 0x30, 0x7, 0, 420),
437435 	CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
438436 		  CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
439
-		  0x47, 0x10, 4, 0x7, 0, 350),
437
+		  0x47, 0x10, 0x7, 0, 350),
440438 	CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
441439 		  CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
442
-		  0x87, 0x30, 4, 0x3, 0, 420),
440
+		  0x87, 0x30, 0x3, 0, 420),
443441 	CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
444442 		  CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
445
-		  0x87, 0x30, 4, 0x5, 0, 420),
443
+		  0x87, 0x30, 0x5, 0, 420),
446444 	CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
447445 		  CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
448
-		  0x80, 0xf, 0, 0x80, 0, 420),
446
+		  0x80, 0xf, 0x80, 0, 420),
449447 	CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
450448 		  CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
451
-		  0x17, 0, 0, 0x2, 0, 0),
449
+		  0x17, 0, 0x2, 0, 0),
452450 	CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
453451 		  CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
454
-		  0x87, 0x38, 3, 0x2, 0, 420),
452
+		  0x87, 0x38, 0x2, 0, 420),
455453 	CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
456454 		  CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
457
-		  0x43, 0x18, 3, 0x1, 0, 420),
455
+		  0x43, 0x18, 0x1, 0, 420),
458456 	CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
459457 		  CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
460
-		  0xac, 0x2, 1, 0xc, 0, 10),
458
+		  0xac, 0x2, 0xc, 0, 10),
461459 	CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
462460 		  CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
463
-		  0x23, 0x8, 3, 0x3, 0, 10),
461
+		  0x23, 0x8, 0x3, 0, 10),
464462 	CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
465463 		  CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
466
-		  0x23, 0x8, 3, 0x3, 0, 420),
464
+		  0x23, 0x8, 0x3, 0, 420),
467465 	CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
468466 		  CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
469
-		  0x47, 0x10, 4, 0x5, 0, 420),
467
+		  0x47, 0x10, 0x5, 0, 420),
470468 	CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
471469 		  CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
472
-		  0x20c, 0xc0, 6, 0x8, 0, 420),
470
+		  0x20c, 0xc0, 0x8, 0, 420),
473471 	CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
474472 		  0xffff, vsim_val_tbl,
475
-		  0x23, 0x8, 3, 0x3, 0, 420),
473
+		  0x23, 0x8, 0x3, 0, 420),
476474 	CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
477475 		  0xffff, vsimcard_val_tbl,
478
-		  0x1e80, 0x8, 3, 0x1e00, 0, 420),
476
+		  0x1e80, 0x8, 0x1e00, 0, 420),
479477 	CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
480478 		  CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
481
-		  0x1, 0xc, 2, 0, 0x1, 500),
479
+		  0x1, 0xc, 0, 0x1, 500),
482480 	CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
483481 		  CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
484
-		  0x11c, 0x40, 6, 0xc, 0, 0),
482
+		  0x11c, 0x40, 0xc, 0, 0),
485483 	CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
486484 		  CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
487
-		  0x16, 0x1, 0, 0x4, 0, 0),
485
+		  0x16, 0x1, 0x4, 0, 0),
488486 	{ /* sentinel */ },
489487 };
490488 
....@@ -507,17 +505,12 @@
507505 static int cpcap_regulator_probe(struct platform_device *pdev)
508506 {
509507 	struct cpcap_ddata *ddata;
510
-	const struct of_device_id *match;
508
+	const struct cpcap_regulator *match_data;
511509 	struct regulator_config config;
512
-	struct regulator_init_data init_data;
513510 	int i;
514511 
515
-	match = of_match_device(of_match_ptr(cpcap_regulator_id_table),
516
-				&pdev->dev);
517
-	if (!match)
518
-		return -EINVAL;
519
-
520
-	if (!match->data) {
512
+	match_data = of_device_get_match_data(&pdev->dev);
513
+	if (!match_data) {
521514 		dev_err(&pdev->dev, "no configuration data found\n");
522515 
523516 		return -ENODEV;
....@@ -532,14 +525,12 @@
532525 		return -ENODEV;
533526 
534527 	ddata->dev = &pdev->dev;
535
-	ddata->soc = match->data;
528
+	ddata->soc = match_data;
536529 	platform_set_drvdata(pdev, ddata);
537530 
538531 	memset(&config, 0, sizeof(config));
539
-	memset(&init_data, 0, sizeof(init_data));
540532 	config.dev = &pdev->dev;
541533 	config.regmap = ddata->reg;
542
-	config.init_data = &init_data;
543534 
544535 	for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
545536 		const struct cpcap_regulator *regulator = &ddata->soc[i];