| .. | .. |
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| 147 | 147 | return err; |
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| 148 | 148 | } |
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| 149 | 149 | |
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| 150 | | - return pwm_set_chip_data(pwm, channel); |
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| 150 | + return 0; |
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| 151 | 151 | } |
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| 152 | 152 | |
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| 153 | 153 | static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
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| 154 | 154 | { |
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| 155 | | - struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
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| 155 | + struct meson_pwm *meson = to_meson_pwm(chip); |
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| 156 | + struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
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| 156 | 157 | |
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| 157 | 158 | if (channel) |
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| 158 | 159 | clk_disable_unprepare(channel->clk); |
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| .. | .. |
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| 161 | 162 | static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, |
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| 162 | 163 | const struct pwm_state *state) |
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| 163 | 164 | { |
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| 164 | | - struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
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| 165 | | - unsigned int duty, period, pre_div, cnt, duty_cnt; |
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| 165 | + struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
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| 166 | + unsigned int pre_div, cnt, duty_cnt; |
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| 166 | 167 | unsigned long fin_freq; |
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| 168 | + u64 duty, period; |
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| 167 | 169 | |
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| 168 | 170 | duty = state->duty_cycle; |
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| 169 | 171 | period = state->period; |
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| 170 | 172 | |
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| 173 | + /* |
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| 174 | + * Note this is wrong. The result is an output wave that isn't really |
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| 175 | + * inverted and so is wrongly identified by .get_state as normal. |
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| 176 | + * Fixing this needs some care however as some machines might rely on |
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| 177 | + * this. |
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| 178 | + */ |
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| 171 | 179 | if (state->polarity == PWM_POLARITY_INVERSED) |
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| 172 | 180 | duty = period - duty; |
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| 173 | 181 | |
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| .. | .. |
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| 179 | 187 | |
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| 180 | 188 | dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); |
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| 181 | 189 | |
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| 182 | | - pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL); |
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| 190 | + pre_div = div64_u64(fin_freq * period, NSEC_PER_SEC * 0xffffLL); |
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| 183 | 191 | if (pre_div > MISC_CLK_DIV_MASK) { |
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| 184 | 192 | dev_err(meson->chip.dev, "unable to get period pre_div\n"); |
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| 185 | 193 | return -EINVAL; |
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| 186 | 194 | } |
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| 187 | 195 | |
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| 188 | | - cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1)); |
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| 196 | + cnt = div64_u64(fin_freq * period, NSEC_PER_SEC * (pre_div + 1)); |
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| 189 | 197 | if (cnt > 0xffff) { |
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| 190 | 198 | dev_err(meson->chip.dev, "unable to get period cnt\n"); |
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| 191 | 199 | return -EINVAL; |
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| 192 | 200 | } |
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| 193 | 201 | |
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| 194 | | - dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, |
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| 202 | + dev_dbg(meson->chip.dev, "period=%llu pre_div=%u cnt=%u\n", period, |
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| 195 | 203 | pre_div, cnt); |
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| 196 | 204 | |
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| 197 | 205 | if (duty == period) { |
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| .. | .. |
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| 204 | 212 | channel->lo = cnt; |
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| 205 | 213 | } else { |
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| 206 | 214 | /* Then check is we can have the duty with the same pre_div */ |
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| 207 | | - duty_cnt = div64_u64(fin_freq * (u64)duty, |
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| 208 | | - NSEC_PER_SEC * (pre_div + 1)); |
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| 215 | + duty_cnt = div64_u64(fin_freq * duty, NSEC_PER_SEC * (pre_div + 1)); |
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| 209 | 216 | if (duty_cnt > 0xffff) { |
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| 210 | 217 | dev_err(meson->chip.dev, "unable to get duty cycle\n"); |
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| 211 | 218 | return -EINVAL; |
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| 212 | 219 | } |
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| 213 | 220 | |
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| 214 | | - dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n", |
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| 221 | + dev_dbg(meson->chip.dev, "duty=%llu pre_div=%u duty_cnt=%u\n", |
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| 215 | 222 | duty, pre_div, duty_cnt); |
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| 216 | 223 | |
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| 217 | 224 | channel->pre_div = pre_div; |
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| .. | .. |
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| 224 | 231 | |
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| 225 | 232 | static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) |
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| 226 | 233 | { |
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| 227 | | - struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
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| 234 | + struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
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| 228 | 235 | struct meson_pwm_channel_data *channel_data; |
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| 229 | 236 | unsigned long flags; |
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| 230 | 237 | u32 value; |
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| .. | .. |
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| 267 | 274 | static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
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| 268 | 275 | const struct pwm_state *state) |
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| 269 | 276 | { |
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| 270 | | - struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); |
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| 271 | 277 | struct meson_pwm *meson = to_meson_pwm(chip); |
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| 278 | + struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; |
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| 272 | 279 | int err = 0; |
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| 273 | 280 | |
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| 274 | 281 | if (!state) |
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| .. | .. |
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| 366 | 373 | state->period = 0; |
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| 367 | 374 | state->duty_cycle = 0; |
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| 368 | 375 | } |
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| 376 | + state->polarity = PWM_POLARITY_NORMAL; |
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| 369 | 377 | } |
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| 370 | 378 | |
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| 371 | 379 | static const struct pwm_ops meson_pwm_ops = { |
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| .. | .. |
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| 417 | 425 | }; |
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| 418 | 426 | |
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| 419 | 427 | static const char * const pwm_axg_ao_parent_names[] = { |
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| 420 | | - "aoclk81", "xtal", "fclk_div4", "fclk_div5" |
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| 428 | + "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" |
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| 421 | 429 | }; |
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| 422 | 430 | |
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| 423 | 431 | static const struct meson_pwm_data pwm_axg_ao_data = { |
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| .. | .. |
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| 426 | 434 | }; |
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| 427 | 435 | |
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| 428 | 436 | static const char * const pwm_g12a_ao_ab_parent_names[] = { |
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| 429 | | - "xtal", "aoclk81", "fclk_div4", "fclk_div5" |
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| 437 | + "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" |
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| 430 | 438 | }; |
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| 431 | 439 | |
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| 432 | 440 | static const struct meson_pwm_data pwm_g12a_ao_ab_data = { |
|---|
| .. | .. |
|---|
| 435 | 443 | }; |
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| 436 | 444 | |
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| 437 | 445 | static const char * const pwm_g12a_ao_cd_parent_names[] = { |
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| 438 | | - "xtal", "aoclk81", |
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| 446 | + "xtal", "g12a_ao_clk81", |
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| 439 | 447 | }; |
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| 440 | 448 | |
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| 441 | 449 | static const struct meson_pwm_data pwm_g12a_ao_cd_data = { |
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