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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/pwm/pwm-mediatek.c
....@@ -1,12 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * Mediatek Pulse Width Modulator driver
3
+ * MediaTek Pulse Width Modulator driver
34  *
45  * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
56  * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
67  *
7
- * This file is licensed under the terms of the GNU General Public
8
- * License version 2. This program is licensed "as is" without any
9
- * warranty of any kind, whether express or implied.
108  */
119 
1210 #include <linux/err.h>
....@@ -35,125 +33,108 @@
3533 
3634 #define PWM_CLK_DIV_MAX		7
3735 
38
-enum {
39
-	MTK_CLK_MAIN = 0,
40
-	MTK_CLK_TOP,
41
-	MTK_CLK_PWM1,
42
-	MTK_CLK_PWM2,
43
-	MTK_CLK_PWM3,
44
-	MTK_CLK_PWM4,
45
-	MTK_CLK_PWM5,
46
-	MTK_CLK_PWM6,
47
-	MTK_CLK_PWM7,
48
-	MTK_CLK_PWM8,
49
-	MTK_CLK_MAX,
50
-};
51
-
52
-static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
53
-	"main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
54
-	"pwm8"
55
-};
56
-
57
-struct mtk_pwm_platform_data {
36
+struct pwm_mediatek_of_data {
5837 	unsigned int num_pwms;
5938 	bool pwm45_fixup;
60
-	bool has_clks;
6139 };
6240 
6341 /**
64
- * struct mtk_pwm_chip - struct representing PWM chip
42
+ * struct pwm_mediatek_chip - struct representing PWM chip
6543  * @chip: linux PWM chip representation
6644  * @regs: base address of PWM chip
67
- * @clks: list of clocks
45
+ * @clk_top: the top clock generator
46
+ * @clk_main: the clock used by PWM core
47
+ * @clk_pwms: the clock used by each PWM channel
48
+ * @clk_freq: the fix clock frequency of legacy MIPS SoC
49
+ * @soc: pointer to chip's platform data
6850  */
69
-struct mtk_pwm_chip {
51
+struct pwm_mediatek_chip {
7052 	struct pwm_chip chip;
7153 	void __iomem *regs;
72
-	struct clk *clks[MTK_CLK_MAX];
73
-	const struct mtk_pwm_platform_data *soc;
54
+	struct clk *clk_top;
55
+	struct clk *clk_main;
56
+	struct clk **clk_pwms;
57
+	const struct pwm_mediatek_of_data *soc;
7458 };
7559 
76
-static const unsigned int mtk_pwm_reg_offset[] = {
60
+static const unsigned int pwm_mediatek_reg_offset[] = {
7761 	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
7862 };
7963 
80
-static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
64
+static inline struct pwm_mediatek_chip *
65
+to_pwm_mediatek_chip(struct pwm_chip *chip)
8166 {
82
-	return container_of(chip, struct mtk_pwm_chip, chip);
67
+	return container_of(chip, struct pwm_mediatek_chip, chip);
8368 }
8469 
85
-static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm)
70
+static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
71
+				   struct pwm_device *pwm)
8672 {
87
-	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
73
+	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
8874 	int ret;
8975 
90
-	if (!pc->soc->has_clks)
91
-		return 0;
92
-
93
-	ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
76
+	ret = clk_prepare_enable(pc->clk_top);
9477 	if (ret < 0)
9578 		return ret;
9679 
97
-	ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
80
+	ret = clk_prepare_enable(pc->clk_main);
9881 	if (ret < 0)
9982 		goto disable_clk_top;
10083 
101
-	ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
84
+	ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
10285 	if (ret < 0)
10386 		goto disable_clk_main;
10487 
10588 	return 0;
10689 
10790 disable_clk_main:
108
-	clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
91
+	clk_disable_unprepare(pc->clk_main);
10992 disable_clk_top:
110
-	clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
93
+	clk_disable_unprepare(pc->clk_top);
11194 
11295 	return ret;
11396 }
11497 
115
-static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm)
98
+static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
99
+				     struct pwm_device *pwm)
116100 {
117
-	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
101
+	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
118102 
119
-	if (!pc->soc->has_clks)
120
-		return;
121
-
122
-	clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
123
-	clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
124
-	clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
103
+	clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
104
+	clk_disable_unprepare(pc->clk_main);
105
+	clk_disable_unprepare(pc->clk_top);
125106 }
126107 
127
-static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
128
-				unsigned int offset)
108
+static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
109
+				     unsigned int num, unsigned int offset)
129110 {
130
-	return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
111
+	return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
131112 }
132113 
133
-static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
134
-				  unsigned int num, unsigned int offset,
135
-				  u32 value)
114
+static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
115
+				       unsigned int num, unsigned int offset,
116
+				       u32 value)
136117 {
137
-	writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
118
+	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
138119 }
139120 
140
-static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
141
-			  int duty_ns, int period_ns)
121
+static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
122
+			       int duty_ns, int period_ns)
142123 {
143
-	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
144
-	struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
124
+	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
145125 	u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
146126 	    reg_thres = PWMTHRES;
147127 	u64 resolution;
148128 	int ret;
149129 
150
-	ret = mtk_pwm_clk_enable(chip, pwm);
130
+	ret = pwm_mediatek_clk_enable(chip, pwm);
131
+
151132 	if (ret < 0)
152133 		return ret;
153134 
154135 	/* Using resolution in picosecond gets accuracy higher */
155136 	resolution = (u64)NSEC_PER_SEC * 1000;
156
-	do_div(resolution, clk_get_rate(clk));
137
+	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
157138 
158139 	cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
159140 	while (cnt_period > 8191) {
....@@ -164,7 +145,7 @@
164145 	}
165146 
166147 	if (clkdiv > PWM_CLK_DIV_MAX) {
167
-		mtk_pwm_clk_disable(chip, pwm);
148
+		pwm_mediatek_clk_disable(chip, pwm);
168149 		dev_err(chip->dev, "period %d not supported\n", period_ns);
169150 		return -EINVAL;
170151 	}
....@@ -179,22 +160,22 @@
179160 	}
180161 
181162 	cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
182
-	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
183
-	mtk_pwm_writel(pc, pwm->hwpwm, reg_width, cnt_period);
184
-	mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
163
+	pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
164
+	pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
165
+	pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
185166 
186
-	mtk_pwm_clk_disable(chip, pwm);
167
+	pwm_mediatek_clk_disable(chip, pwm);
187168 
188169 	return 0;
189170 }
190171 
191
-static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
172
+static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
192173 {
193
-	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
174
+	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
194175 	u32 value;
195176 	int ret;
196177 
197
-	ret = mtk_pwm_clk_enable(chip, pwm);
178
+	ret = pwm_mediatek_clk_enable(chip, pwm);
198179 	if (ret < 0)
199180 		return ret;
200181 
....@@ -205,29 +186,28 @@
205186 	return 0;
206187 }
207188 
208
-static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
189
+static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
209190 {
210
-	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
191
+	struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
211192 	u32 value;
212193 
213194 	value = readl(pc->regs);
214195 	value &= ~BIT(pwm->hwpwm);
215196 	writel(value, pc->regs);
216197 
217
-	mtk_pwm_clk_disable(chip, pwm);
198
+	pwm_mediatek_clk_disable(chip, pwm);
218199 }
219200 
220
-static const struct pwm_ops mtk_pwm_ops = {
221
-	.config = mtk_pwm_config,
222
-	.enable = mtk_pwm_enable,
223
-	.disable = mtk_pwm_disable,
201
+static const struct pwm_ops pwm_mediatek_ops = {
202
+	.config = pwm_mediatek_config,
203
+	.enable = pwm_mediatek_enable,
204
+	.disable = pwm_mediatek_disable,
224205 	.owner = THIS_MODULE,
225206 };
226207 
227
-static int mtk_pwm_probe(struct platform_device *pdev)
208
+static int pwm_mediatek_probe(struct platform_device *pdev)
228209 {
229
-	const struct mtk_pwm_platform_data *data;
230
-	struct mtk_pwm_chip *pc;
210
+	struct pwm_mediatek_chip *pc;
231211 	struct resource *res;
232212 	unsigned int i;
233213 	int ret;
....@@ -236,31 +216,51 @@
236216 	if (!pc)
237217 		return -ENOMEM;
238218 
239
-	data = of_device_get_match_data(&pdev->dev);
240
-	if (data == NULL)
241
-		return -EINVAL;
242
-	pc->soc = data;
219
+	pc->soc = of_device_get_match_data(&pdev->dev);
243220 
244221 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
245222 	pc->regs = devm_ioremap_resource(&pdev->dev, res);
246223 	if (IS_ERR(pc->regs))
247224 		return PTR_ERR(pc->regs);
248225 
249
-	for (i = 0; i < data->num_pwms + 2 && pc->soc->has_clks; i++) {
250
-		pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
251
-		if (IS_ERR(pc->clks[i])) {
226
+	pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
227
+				    sizeof(*pc->clk_pwms), GFP_KERNEL);
228
+	if (!pc->clk_pwms)
229
+		return -ENOMEM;
230
+
231
+	pc->clk_top = devm_clk_get(&pdev->dev, "top");
232
+	if (IS_ERR(pc->clk_top)) {
233
+		dev_err(&pdev->dev, "clock: top fail: %ld\n",
234
+			PTR_ERR(pc->clk_top));
235
+		return PTR_ERR(pc->clk_top);
236
+	}
237
+
238
+	pc->clk_main = devm_clk_get(&pdev->dev, "main");
239
+	if (IS_ERR(pc->clk_main)) {
240
+		dev_err(&pdev->dev, "clock: main fail: %ld\n",
241
+			PTR_ERR(pc->clk_main));
242
+		return PTR_ERR(pc->clk_main);
243
+	}
244
+
245
+	for (i = 0; i < pc->soc->num_pwms; i++) {
246
+		char name[8];
247
+
248
+		snprintf(name, sizeof(name), "pwm%d", i + 1);
249
+
250
+		pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
251
+		if (IS_ERR(pc->clk_pwms[i])) {
252252 			dev_err(&pdev->dev, "clock: %s fail: %ld\n",
253
-				mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
254
-			return PTR_ERR(pc->clks[i]);
253
+				name, PTR_ERR(pc->clk_pwms[i]));
254
+			return PTR_ERR(pc->clk_pwms[i]);
255255 		}
256256 	}
257257 
258258 	platform_set_drvdata(pdev, pc);
259259 
260260 	pc->chip.dev = &pdev->dev;
261
-	pc->chip.ops = &mtk_pwm_ops;
261
+	pc->chip.ops = &pwm_mediatek_ops;
262262 	pc->chip.base = -1;
263
-	pc->chip.npwm = data->num_pwms;
263
+	pc->chip.npwm = pc->soc->num_pwms;
264264 
265265 	ret = pwmchip_add(&pc->chip);
266266 	if (ret < 0) {
....@@ -271,55 +271,63 @@
271271 	return 0;
272272 }
273273 
274
-static int mtk_pwm_remove(struct platform_device *pdev)
274
+static int pwm_mediatek_remove(struct platform_device *pdev)
275275 {
276
-	struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
276
+	struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
277277 
278278 	return pwmchip_remove(&pc->chip);
279279 }
280280 
281
-static const struct mtk_pwm_platform_data mt2712_pwm_data = {
281
+static const struct pwm_mediatek_of_data mt2712_pwm_data = {
282282 	.num_pwms = 8,
283283 	.pwm45_fixup = false,
284
-	.has_clks = true,
285284 };
286285 
287
-static const struct mtk_pwm_platform_data mt7622_pwm_data = {
286
+static const struct pwm_mediatek_of_data mt7622_pwm_data = {
288287 	.num_pwms = 6,
289288 	.pwm45_fixup = false,
290
-	.has_clks = true,
291289 };
292290 
293
-static const struct mtk_pwm_platform_data mt7623_pwm_data = {
291
+static const struct pwm_mediatek_of_data mt7623_pwm_data = {
294292 	.num_pwms = 5,
295293 	.pwm45_fixup = true,
296
-	.has_clks = true,
297294 };
298295 
299
-static const struct mtk_pwm_platform_data mt7628_pwm_data = {
296
+static const struct pwm_mediatek_of_data mt7628_pwm_data = {
300297 	.num_pwms = 4,
301298 	.pwm45_fixup = true,
302
-	.has_clks = false,
303299 };
304300 
305
-static const struct of_device_id mtk_pwm_of_match[] = {
301
+static const struct pwm_mediatek_of_data mt7629_pwm_data = {
302
+	.num_pwms = 1,
303
+	.pwm45_fixup = false,
304
+};
305
+
306
+static const struct pwm_mediatek_of_data mt8516_pwm_data = {
307
+	.num_pwms = 5,
308
+	.pwm45_fixup = false,
309
+};
310
+
311
+static const struct of_device_id pwm_mediatek_of_match[] = {
306312 	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
307313 	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
308314 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
309315 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
316
+	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
317
+	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
310318 	{ },
311319 };
312
-MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
320
+MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
313321 
314
-static struct platform_driver mtk_pwm_driver = {
322
+static struct platform_driver pwm_mediatek_driver = {
315323 	.driver = {
316
-		.name = "mtk-pwm",
317
-		.of_match_table = mtk_pwm_of_match,
324
+		.name = "pwm-mediatek",
325
+		.of_match_table = pwm_mediatek_of_match,
318326 	},
319
-	.probe = mtk_pwm_probe,
320
-	.remove = mtk_pwm_remove,
327
+	.probe = pwm_mediatek_probe,
328
+	.remove = pwm_mediatek_remove,
321329 };
322
-module_platform_driver(mtk_pwm_driver);
330
+module_platform_driver(pwm_mediatek_driver);
323331 
324332 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
325
-MODULE_LICENSE("GPL");
333
+MODULE_LICENSE("GPL v2");