change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/pwm/pwm-lpss.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Intel Low Power Subsystem PWM controller driver
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  *
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@@ -7,10 +8,6 @@
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  * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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  * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
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  * Author: Alan Cox <alan@linux.intel.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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12
 
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 #include <linux/delay.h>
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@@ -31,15 +28,6 @@
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28
 
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 /* Size of each PWM register space if multiple */
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 #define PWM_SIZE			0x400
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-
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-#define MAX_PWMS			4
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-
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-struct pwm_lpss_chip {
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-	struct pwm_chip chip;
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-	void __iomem *regs;
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-	const struct pwm_lpss_boardinfo *info;
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-	u32 saved_ctrl[MAX_PWMS];
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-};
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 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
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 {
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@@ -97,7 +85,7 @@
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 	unsigned long long on_time_div;
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 	unsigned long c = lpwm->info->clk_rate, base_unit_range;
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 	unsigned long long base_unit, freq = NSEC_PER_SEC;
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-	u32 orig_ctrl, ctrl;
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+	u32 ctrl;
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 	do_div(freq, period_ns);
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@@ -116,16 +104,14 @@
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 	do_div(on_time_div, period_ns);
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 	on_time_div = 255ULL - on_time_div;
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-	orig_ctrl = ctrl = pwm_lpss_read(pwm);
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+	ctrl = pwm_lpss_read(pwm);
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 	ctrl &= ~PWM_ON_TIME_DIV_MASK;
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 	ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
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 	ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
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 	ctrl |= on_time_div;
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-	if (orig_ctrl != ctrl) {
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-		pwm_lpss_write(pwm, ctrl);
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-		pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
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-	}
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+	pwm_lpss_write(pwm, ctrl);
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+	pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
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 }
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 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
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@@ -134,45 +120,85 @@
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 		pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
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 }
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+static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
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+				   struct pwm_device *pwm,
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+				   const struct pwm_state *state)
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+{
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+	int ret;
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+
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+	ret = pwm_lpss_is_updating(pwm);
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+	if (ret)
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+		return ret;
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+
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+	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
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+	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
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+	ret = pwm_lpss_wait_for_update(pwm);
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+	if (ret)
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+		return ret;
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+
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+	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
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+	return 0;
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+}
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+
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 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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-			  struct pwm_state *state)
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+			  const struct pwm_state *state)
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 {
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 	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
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-	int ret;
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+	int ret = 0;
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 	if (state->enabled) {
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 		if (!pwm_is_enabled(pwm)) {
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 			pm_runtime_get_sync(chip->dev);
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-			ret = pwm_lpss_is_updating(pwm);
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-			if (ret) {
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-				pm_runtime_put(chip->dev);
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-				return ret;
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-			}
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-			pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
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-			pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
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-			ret = pwm_lpss_wait_for_update(pwm);
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-			if (ret) {
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-				pm_runtime_put(chip->dev);
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-				return ret;
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-			}
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-			pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
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-		} else {
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-			ret = pwm_lpss_is_updating(pwm);
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+			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
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 			if (ret)
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-				return ret;
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-			pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
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-			return pwm_lpss_wait_for_update(pwm);
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+				pm_runtime_put(chip->dev);
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+		} else {
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+			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
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 		}
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 	} else if (pwm_is_enabled(pwm)) {
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 		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
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 		pm_runtime_put(chip->dev);
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 	}
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-	return 0;
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+	return ret;
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+}
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+
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+static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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+			       struct pwm_state *state)
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+{
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+	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
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+	unsigned long base_unit_range;
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+	unsigned long long base_unit, freq, on_time_div;
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+	u32 ctrl;
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+
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+	pm_runtime_get_sync(chip->dev);
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+
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+	base_unit_range = BIT(lpwm->info->base_unit_bits);
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+
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+	ctrl = pwm_lpss_read(pwm);
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+	on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
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+	base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
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+
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+	freq = base_unit * lpwm->info->clk_rate;
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+	do_div(freq, base_unit_range);
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+	if (freq == 0)
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+		state->period = NSEC_PER_SEC;
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+	else
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+		state->period = NSEC_PER_SEC / (unsigned long)freq;
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+
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+	on_time_div *= state->period;
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+	do_div(on_time_div, 255);
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+	state->duty_cycle = on_time_div;
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+
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+	state->polarity = PWM_POLARITY_NORMAL;
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+	state->enabled = !!(ctrl & PWM_ENABLE);
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+
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+	pm_runtime_put(chip->dev);
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 }
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 static const struct pwm_ops pwm_lpss_ops = {
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 	.apply = pwm_lpss_apply,
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+	.get_state = pwm_lpss_get_state,
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 	.owner = THIS_MODULE,
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 };
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@@ -181,7 +207,8 @@
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 {
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 	struct pwm_lpss_chip *lpwm;
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 	unsigned long c;
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-	int ret;
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+	int i, ret;
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+	u32 ctrl;
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 	if (WARN_ON(info->npwm > MAX_PWMS))
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 		return ERR_PTR(-ENODEV);
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@@ -211,6 +238,12 @@
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 		return ERR_PTR(ret);
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 	}
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+	for (i = 0; i < lpwm->info->npwm; i++) {
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+		ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
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+		if (ctrl & PWM_ENABLE)
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+			pm_runtime_get(dev);
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+	}
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+
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 	return lpwm;
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 }
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 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
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@@ -226,30 +259,6 @@
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 	return pwmchip_remove(&lpwm->chip);
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 }
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 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
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-
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-int pwm_lpss_suspend(struct device *dev)
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-{
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-	struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
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-	int i;
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-
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-	for (i = 0; i < lpwm->info->npwm; i++)
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-		lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
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-
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-	return 0;
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-}
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-EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
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-
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-int pwm_lpss_resume(struct device *dev)
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-{
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-	struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
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-	int i;
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-
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-	for (i = 0; i < lpwm->info->npwm; i++)
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-		writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
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-
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-	return 0;
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-}
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-EXPORT_SYMBOL_GPL(pwm_lpss_resume);
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 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
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 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");