~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,13 +1,191 @@
1	1	/* SPDX-License-Identifier: GPL-2.0-only */
2	2	/*
3		- * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
	3	+ * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
	4	+ *
	5	+ * Copyright (c) 2013 MundoReader S.L.
	6	+ * Author: Heiko Stuebner <heiko@sntech.de>
	7	+ *
	8	+ * With some ideas taken from pinctrl-samsung:
	9	+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
	10	+ * http://www.samsung.com
	11	+ * Copyright (c) 2012 Linaro Ltd
	12	+ * https://www.linaro.org
	13	+ *
	14	+ * and pinctrl-at91:
	15	+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4	16	*/
5	17
6	18	#ifndef _PINCTRL_ROCKCHIP_H
7	19	#define _PINCTRL_ROCKCHIP_H
8	20
	21	+#define RK_GPIO0_A0 0
	22	+#define RK_GPIO0_A1 1
	23	+#define RK_GPIO0_A2 2
	24	+#define RK_GPIO0_A3 3
	25	+#define RK_GPIO0_A4 4
	26	+#define RK_GPIO0_A5 5
	27	+#define RK_GPIO0_A6 6
	28	+#define RK_GPIO0_A7 7
	29	+#define RK_GPIO0_B0 8
	30	+#define RK_GPIO0_B1 9
	31	+#define RK_GPIO0_B2 10
	32	+#define RK_GPIO0_B3 11
	33	+#define RK_GPIO0_B4 12
	34	+#define RK_GPIO0_B5 13
	35	+#define RK_GPIO0_B6 14
	36	+#define RK_GPIO0_B7 15
	37	+#define RK_GPIO0_C0 16
	38	+#define RK_GPIO0_C1 17
	39	+#define RK_GPIO0_C2 18
	40	+#define RK_GPIO0_C3 19
	41	+#define RK_GPIO0_C4 20
	42	+#define RK_GPIO0_C5 21
	43	+#define RK_GPIO0_C6 22
	44	+#define RK_GPIO0_C7 23
	45	+#define RK_GPIO0_D0 24
	46	+#define RK_GPIO0_D1 25
	47	+#define RK_GPIO0_D2 26
	48	+#define RK_GPIO0_D3 27
	49	+#define RK_GPIO0_D4 28
	50	+#define RK_GPIO0_D5 29
	51	+#define RK_GPIO0_D6 30
	52	+#define RK_GPIO0_D7 31
	53	+
	54	+#define RK_GPIO1_A0 32
	55	+#define RK_GPIO1_A1 33
	56	+#define RK_GPIO1_A2 34
	57	+#define RK_GPIO1_A3 35
	58	+#define RK_GPIO1_A4 36
	59	+#define RK_GPIO1_A5 37
	60	+#define RK_GPIO1_A6 38
	61	+#define RK_GPIO1_A7 39
	62	+#define RK_GPIO1_B0 40
	63	+#define RK_GPIO1_B1 41
	64	+#define RK_GPIO1_B2 42
	65	+#define RK_GPIO1_B3 43
	66	+#define RK_GPIO1_B4 44
	67	+#define RK_GPIO1_B5 45
	68	+#define RK_GPIO1_B6 46
	69	+#define RK_GPIO1_B7 47
	70	+#define RK_GPIO1_C0 48
	71	+#define RK_GPIO1_C1 49
	72	+#define RK_GPIO1_C2 50
	73	+#define RK_GPIO1_C3 51
	74	+#define RK_GPIO1_C4 52
	75	+#define RK_GPIO1_C5 53
	76	+#define RK_GPIO1_C6 54
	77	+#define RK_GPIO1_C7 55
	78	+#define RK_GPIO1_D0 56
	79	+#define RK_GPIO1_D1 57
	80	+#define RK_GPIO1_D2 58
	81	+#define RK_GPIO1_D3 59
	82	+#define RK_GPIO1_D4 60
	83	+#define RK_GPIO1_D5 61
	84	+#define RK_GPIO1_D6 62
	85	+#define RK_GPIO1_D7 63
	86	+
	87	+#define RK_GPIO2_A0 64
	88	+#define RK_GPIO2_A1 65
	89	+#define RK_GPIO2_A2 66
	90	+#define RK_GPIO2_A3 67
	91	+#define RK_GPIO2_A4 68
	92	+#define RK_GPIO2_A5 69
	93	+#define RK_GPIO2_A6 70
	94	+#define RK_GPIO2_A7 71
	95	+#define RK_GPIO2_B0 72
	96	+#define RK_GPIO2_B1 73
	97	+#define RK_GPIO2_B2 74
	98	+#define RK_GPIO2_B3 75
	99	+#define RK_GPIO2_B4 76
	100	+#define RK_GPIO2_B5 77
	101	+#define RK_GPIO2_B6 78
	102	+#define RK_GPIO2_B7 79
	103	+#define RK_GPIO2_C0 80
	104	+#define RK_GPIO2_C1 81
	105	+#define RK_GPIO2_C2 82
	106	+#define RK_GPIO2_C3 83
	107	+#define RK_GPIO2_C4 84
	108	+#define RK_GPIO2_C5 85
	109	+#define RK_GPIO2_C6 86
	110	+#define RK_GPIO2_C7 87
	111	+#define RK_GPIO2_D0 88
	112	+#define RK_GPIO2_D1 89
	113	+#define RK_GPIO2_D2 90
	114	+#define RK_GPIO2_D3 91
	115	+#define RK_GPIO2_D4 92
	116	+#define RK_GPIO2_D5 93
	117	+#define RK_GPIO2_D6 94
	118	+#define RK_GPIO2_D7 95
	119	+
	120	+#define RK_GPIO3_A0 96
	121	+#define RK_GPIO3_A1 97
	122	+#define RK_GPIO3_A2 98
	123	+#define RK_GPIO3_A3 99
	124	+#define RK_GPIO3_A4 100
	125	+#define RK_GPIO3_A5 101
	126	+#define RK_GPIO3_A6 102
	127	+#define RK_GPIO3_A7 103
	128	+#define RK_GPIO3_B0 104
	129	+#define RK_GPIO3_B1 105
	130	+#define RK_GPIO3_B2 106
	131	+#define RK_GPIO3_B3 107
	132	+#define RK_GPIO3_B4 108
	133	+#define RK_GPIO3_B5 109
	134	+#define RK_GPIO3_B6 110
	135	+#define RK_GPIO3_B7 111
	136	+#define RK_GPIO3_C0 112
	137	+#define RK_GPIO3_C1 113
	138	+#define RK_GPIO3_C2 114
	139	+#define RK_GPIO3_C3 115
	140	+#define RK_GPIO3_C4 116
	141	+#define RK_GPIO3_C5 117
	142	+#define RK_GPIO3_C6 118
	143	+#define RK_GPIO3_C7 119
	144	+#define RK_GPIO3_D0 120
	145	+#define RK_GPIO3_D1 121
	146	+#define RK_GPIO3_D2 122
	147	+#define RK_GPIO3_D3 123
	148	+#define RK_GPIO3_D4 124
	149	+#define RK_GPIO3_D5 125
	150	+#define RK_GPIO3_D6 126
	151	+#define RK_GPIO3_D7 127
	152	+
	153	+#define RK_GPIO4_A0 128
	154	+#define RK_GPIO4_A1 129
	155	+#define RK_GPIO4_A2 130
	156	+#define RK_GPIO4_A3 131
	157	+#define RK_GPIO4_A4 132
	158	+#define RK_GPIO4_A5 133
	159	+#define RK_GPIO4_A6 134
	160	+#define RK_GPIO4_A7 135
	161	+#define RK_GPIO4_B0 136
	162	+#define RK_GPIO4_B1 137
	163	+#define RK_GPIO4_B2 138
	164	+#define RK_GPIO4_B3 139
	165	+#define RK_GPIO4_B4 140
	166	+#define RK_GPIO4_B5 141
	167	+#define RK_GPIO4_B6 142
	168	+#define RK_GPIO4_B7 143
	169	+#define RK_GPIO4_C0 144
	170	+#define RK_GPIO4_C1 145
	171	+#define RK_GPIO4_C2 146
	172	+#define RK_GPIO4_C3 147
	173	+#define RK_GPIO4_C4 148
	174	+#define RK_GPIO4_C5 149
	175	+#define RK_GPIO4_C6 150
	176	+#define RK_GPIO4_C7 151
	177	+#define RK_GPIO4_D0 152
	178	+#define RK_GPIO4_D1 153
	179	+#define RK_GPIO4_D2 154
	180	+#define RK_GPIO4_D3 155
	181	+#define RK_GPIO4_D4 156
	182	+#define RK_GPIO4_D5 157
	183	+#define RK_GPIO4_D6 158
	184	+#define RK_GPIO4_D7 159
	185	+
9	186	enum rockchip_pinctrl_type {
10	187	PX30,
	188	+ RV1106,
11	189	RV1108,
12	190	RV1126,
13	191	RK1808,
..	..	@@ -20,9 +198,29 @@
20	198	RK3368,
21	199	RK3399,
22	200	RK3528,
	201	+ RK3562,
23	202	RK3568,
	203	+ RK3588,
24	204	};
25	205
	206	+/**
	207	+ * struct rockchip_gpio_regs
	208	+ * @port_dr: data register
	209	+ * @port_ddr: data direction register
	210	+ * @int_en: interrupt enable
	211	+ * @int_mask: interrupt mask
	212	+ * @int_type: interrupt trigger type, such as high, low, edge trriger type.
	213	+ * @int_polarity: interrupt polarity enable register
	214	+ * @int_bothedge: interrupt bothedge enable register
	215	+ * @int_status: interrupt status register
	216	+ * @int_rawstatus: int_status = int_rawstatus & int_mask
	217	+ * @debounce: enable debounce for interrupt signal
	218	+ * @dbclk_div_en: enable divider for debounce clock
	219	+ * @dbclk_div_con: setting for divider of debounce clock
	220	+ * @port_eoi: end of interrupt of the port
	221	+ * @ext_port: port data from external
	222	+ * @version_id: controller version register
	223	+ */
26	224	struct rockchip_gpio_regs {
27	225	u32 port_dr;
28	226	u32 port_ddr;
..	..	@@ -42,6 +240,7 @@
42	240	};
43	241
44	242	/**
	243	+ * struct rockchip_iomux
45	244	* @type: iomux variant using IOMUX_* constants
46	245	* @offset: if initialized to -1 it will be autocalculated, by specifying
47	246	* an initial offset value the relevant source offset can be reset
..	..	@@ -52,7 +251,7 @@
52	251	int offset;
53	252	};
54	253
55		-/**
	254	+/*
56	255	* enum type index corresponding to rockchip_perpin_drv_list arrays index.
57	256	*/
58	257	enum rockchip_pin_drv_type {
..	..	@@ -65,7 +264,7 @@
65	264	DRV_TYPE_MAX
66	265	};
67	266
68		-/**
	267	+/*
69	268	* enum type index corresponding to rockchip_pull_list arrays index.
70	269	*/
71	270	enum rockchip_pin_pull_type {
..	..	@@ -74,13 +273,8 @@
74	273	PULL_TYPE_MAX
75	274	};
76	275
77		-enum rockchip_mux_route_location {
78		- ROCKCHIP_ROUTE_SAME = 0,
79		- ROCKCHIP_ROUTE_PMU,
80		- ROCKCHIP_ROUTE_GRF,
81		-};
82		-
83	276	/**
	277	+ * struct rockchip_drv
84	278	* @drv_type: drive strength variant using rockchip_perpin_drv_type
85	279	* @offset: if initialized to -1 it will be autocalculated, by specifying
86	280	* an initial offset value the relevant source offset can be reset
..	..	@@ -94,9 +288,10 @@
94	288	};
95	289
96	290	/**
97		- * @dev: device of the gpio bank
	291	+ * struct rockchip_pin_bank
	292	+ * @dev: the pinctrl device bind to the bank
98	293	* @reg_base: register base of the gpio bank
99		- * @reg_pull: optional separate register for additional pull settings
	294	+ * @regmap_pull: optional separate register for additional pull settings
100	295	* @clk: clock of the gpio bank
101	296	* @db_clk: clock of the gpio debounce
102	297	* @irq: interrupt of the gpio bank
..	..	@@ -108,17 +303,21 @@
108	303	* @iomux: array describing the 4 iomux sources of the bank
109	304	* @drv: array describing the 4 drive strength sources of the bank
110	305	* @pull_type: array describing the 4 pull type sources of the bank
	306	+ * @valid: is all necessary information present
111	307	* @of_node: dt node of this bank
112	308	* @drvdata: common pinctrl basedata
113	309	* @domain: irqdomain of the gpio bank
114	310	* @gpio_chip: gpiolib chip
115	311	* @grange: gpio range
116	312	* @slock: spinlock for the gpio bank
	313	+ * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
	314	+ * @recalced_mask: bit mask to indicate a need to recalulate the mask
117	315	* @route_mask: bits describing the routing pins of per bank
	316	+ * @deferred_output: gpio output settings to be done after gpio bank probed
	317	+ * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
118	318	*/
119	319	struct rockchip_pin_bank {
120		- struct device *dev;
121		-
	320	+ struct device *dev;
122	321	void __iomem *reg_base;
123	322	struct regmap *regmap_pull;
124	323	struct clk *clk;
..	..	@@ -132,6 +331,7 @@
132	331	struct rockchip_iomux iomux[4];
133	332	struct rockchip_drv drv[4];
134	333	enum rockchip_pin_pull_type pull_type[4];
	334	+ bool valid;
135	335	struct device_node *of_node;
136	336	struct rockchip_pinctrl *drvdata;
137	337	struct irq_domain *domain;
..	..	@@ -143,6 +343,8 @@
143	343	u32 toggle_edge_mode;
144	344	u32 recalced_mask;
145	345	u32 route_mask;
	346	+ struct list_head deferred_pins;
	347	+ struct mutex deferred_lock;
146	348	};
147	349
148	350	/**
..	..	@@ -159,6 +361,12 @@
159	361	u32 reg;
160	362	u8 bit;
161	363	u8 mask;
	364	+};
	365	+
	366	+enum rockchip_mux_route_location {
	367	+ ROCKCHIP_ROUTE_SAME = 0,
	368	+ ROCKCHIP_ROUTE_PMU,
	369	+ ROCKCHIP_ROUTE_GRF,
162	370	};
163	371
164	372	/**
..	..	@@ -194,14 +402,10 @@
194	402	struct rockchip_mux_route_data *iomux_routes;
195	403	u32 niomux_routes;
196	404
197		- int (ctrl_data_re_init)(struct rockchip_pin_ctrl ctrl);
198		-
199		- int (soc_data_init)(struct rockchip_pinctrl info);
200		-
201		- void (pull_calc_reg)(struct rockchip_pin_bank bank,
	405	+ int (pull_calc_reg)(struct rockchip_pin_bank bank,
202	406	int pin_num, struct regmap **regmap,
203	407	int reg, u8 bit);
204		- void (drv_calc_reg)(struct rockchip_pin_bank bank,
	408	+ int (drv_calc_reg)(struct rockchip_pin_bank bank,
205	409	int pin_num, struct regmap **regmap,
206	410	int reg, u8 bit);
207	411	int (schmitt_calc_reg)(struct rockchip_pin_bank bank,
..	..	@@ -218,14 +422,21 @@
218	422	unsigned int nconfigs;
219	423	};
220	424
	425	+enum pin_config_param;
	426	+
	427	+struct rockchip_pin_deferred {
	428	+ struct list_head head;
	429	+ unsigned int pin;
	430	+ enum pin_config_param param;
	431	+ u32 arg;
	432	+};
	433	+
221	434	/**
222	435	* struct rockchip_pin_group: represent group of pins of a pinmux function.
223	436	* @name: name of the pin group, used to lookup the group.
224	437	* @pins: the pins included in this group.
225	438	* @npins: number of pins included in this group.
226		- * @func: the mux function number to be programmed when selected.
227		- * @configs: the config values to be set for each pin
228		- * @nconfigs: number of configs for each pin
	439	+ * @data: local pin configuration
229	440	*/
230	441	struct rockchip_pin_group {
231	442	const char *name;
..	..	@@ -238,7 +449,7 @@
238	449	* struct rockchip_pmx_func: represent a pin function.
239	450	* @name: name of the pin function, used to lookup the function.
240	451	* @groups: one or more names of pin groups that provide this function.
241		- * @num_groups: number of groups included in @groups.
	452	+ * @ngroups: number of groups included in @groups.
242	453	*/
243	454	struct rockchip_pmx_func {
244	455	const char *name;
..	..	@@ -261,4 +472,19 @@
261	472	unsigned int nfunctions;
262	473	};
263	474
	475	+#if IS_ENABLED(CONFIG_PINCTRL_ROCKCHIP)
	476	+int rk_iomux_set(int bank, int pin, int mux);
	477	+int rk_iomux_get(int bank, int pin, int *mux);
	478	+#else
	479	+static inline int rk_iomux_set(int bank, int pin, int mux)
	480	+{
	481	+ return -EINVAL;
	482	+}
	483	+
	484	+static inline int rk_iomux_get(int bank, int pin, int *mux)
	485	+{
	486	+ return -EINVAL;
	487	+}
	488	+#endif
	489	+
264	490	#endif