change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/pinctrl/pinctrl-oxnas.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Oxford Semiconductor OXNAS SoC Family pinctrl driver
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  *
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@@ -6,15 +7,6 @@
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  * Based on pinctrl-pic32.c
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  * Joshua Henderson, <joshua.henderson@microchip.com>
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  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
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- *
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- * This program is free software; you can distribute it and/or modify it
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- * under the terms of the GNU General Public License (Version 2) as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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- * for more details.
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  */
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 #include <linux/gpio/driver.h>
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 #include <linux/interrupt.h>
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@@ -764,7 +756,10 @@
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 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
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 	u32 mask = BIT(offset);
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-	return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask);
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+	if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)
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+		return GPIO_LINE_DIRECTION_OUT;
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+
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+	return GPIO_LINE_DIRECTION_IN;
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 }
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 static int oxnas_gpio_direction_input(struct gpio_chip *chip,
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@@ -910,7 +905,6 @@
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 	struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
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 	unsigned int param;
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-	u32 arg;
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 	unsigned int i;
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 	u32 offset = pin - bank->gpio_chip.base;
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 	u32 mask = BIT(offset);
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@@ -920,7 +914,6 @@
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 	for (i = 0; i < num_configs; i++) {
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 		param = pinconf_to_config_param(configs[i]);
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-		arg = pinconf_to_config_argument(configs[i]);
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 		switch (param) {
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 		case PIN_CONFIG_BIAS_PULL_UP:
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@@ -949,7 +942,6 @@
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 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
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 	unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
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 	unsigned int param;
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-	u32 arg;
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 	unsigned int i;
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 	u32 offset = pin - bank->gpio_chip.base;
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 	u32 mask = BIT(offset);
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@@ -959,7 +951,6 @@
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 	for (i = 0; i < num_configs; i++) {
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 		param = pinconf_to_config_param(configs[i]);
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-		arg = pinconf_to_config_argument(configs[i]);
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954
 
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 		switch (param) {
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 		case PIN_CONFIG_BIAS_PULL_UP:
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@@ -1208,7 +1199,7 @@
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 	struct oxnas_gpio_bank *bank;
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 	unsigned int id, ngpios;
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 	int irq, ret;
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-	struct resource *res;
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+	struct gpio_irq_chip *girq;
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 	if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
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 					     3, 0, &pinspec)) {
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@@ -1231,39 +1222,36 @@
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 	bank = &oxnas_gpio_banks[id];
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
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+	bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(bank->reg_base))
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 		return PTR_ERR(bank->reg_base);
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 	irq = platform_get_irq(pdev, 0);
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-	if (irq < 0) {
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-		dev_err(&pdev->dev, "irq get failed\n");
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+	if (irq < 0)
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 		return irq;
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-	}
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 	bank->id = id;
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 	bank->gpio_chip.parent = &pdev->dev;
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 	bank->gpio_chip.of_node = np;
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 	bank->gpio_chip.ngpio = ngpios;
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+	girq = &bank->gpio_chip.irq;
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+	girq->chip = &bank->irq_chip;
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+	girq->parent_handler = oxnas_gpio_irq_handler;
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+	girq->num_parents = 1;
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+	girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
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+				     GFP_KERNEL);
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+	if (!girq->parents)
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+		return -ENOMEM;
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+	girq->parents[0] = irq;
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+	girq->default_type = IRQ_TYPE_NONE;
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+	girq->handler = handle_level_irq;
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+
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 	ret = gpiochip_add_data(&bank->gpio_chip, bank);
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 	if (ret < 0) {
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 		dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
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 			id, ret);
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 		return ret;
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 	}
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-
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-	ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
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-				0, handle_level_irq, IRQ_TYPE_NONE);
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-	if (ret < 0) {
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-		dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
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-			id, ret);
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-		gpiochip_remove(&bank->gpio_chip);
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-		return ret;
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-	}
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-
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-	gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
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-				     irq, oxnas_gpio_irq_handler);
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 	return 0;
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 }