forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/pinctrl/intel/pinctrl-intel.c
....@@ -7,11 +7,15 @@
77  *          Mika Westerberg <mika.westerberg@linux.intel.com>
88  */
99 
10
-#include <linux/module.h>
11
-#include <linux/interrupt.h>
10
+#include <linux/acpi.h>
1211 #include <linux/gpio/driver.h>
12
+#include <linux/interrupt.h>
1313 #include <linux/log2.h>
14
+#include <linux/module.h>
1415 #include <linux/platform_device.h>
16
+#include <linux/property.h>
17
+#include <linux/time.h>
18
+
1519 #include <linux/pinctrl/pinctrl.h>
1620 #include <linux/pinctrl/pinmux.h>
1721 #include <linux/pinctrl/pinconf.h>
....@@ -26,17 +30,16 @@
2630 #define REVID_MASK			GENMASK(31, 16)
2731 
2832 #define PADBAR				0x00c
29
-#define GPI_IS				0x100
3033 
3134 #define PADOWN_BITS			4
3235 #define PADOWN_SHIFT(p)			((p) % 8 * PADOWN_BITS)
33
-#define PADOWN_MASK(p)			(0xf << PADOWN_SHIFT(p))
36
+#define PADOWN_MASK(p)			(GENMASK(3, 0) << PADOWN_SHIFT(p))
3437 #define PADOWN_GPP(p)			((p) / 8)
3538 
3639 /* Offset from pad_regs */
3740 #define PADCFG0				0x000
3841 #define PADCFG0_RXEVCFG_SHIFT		25
39
-#define PADCFG0_RXEVCFG_MASK		(3 << PADCFG0_RXEVCFG_SHIFT)
42
+#define PADCFG0_RXEVCFG_MASK		GENMASK(26, 25)
4043 #define PADCFG0_RXEVCFG_LEVEL		0
4144 #define PADCFG0_RXEVCFG_EDGE		1
4245 #define PADCFG0_RXEVCFG_DISABLED	2
....@@ -48,7 +51,7 @@
4851 #define PADCFG0_GPIROUTSMI		BIT(18)
4952 #define PADCFG0_GPIROUTNMI		BIT(17)
5053 #define PADCFG0_PMODE_SHIFT		10
51
-#define PADCFG0_PMODE_MASK		(0xf << PADCFG0_PMODE_SHIFT)
54
+#define PADCFG0_PMODE_MASK		GENMASK(13, 10)
5255 #define PADCFG0_PMODE_GPIO		0
5356 #define PADCFG0_GPIORXDIS		BIT(9)
5457 #define PADCFG0_GPIOTXDIS		BIT(8)
....@@ -58,18 +61,18 @@
5861 #define PADCFG1				0x004
5962 #define PADCFG1_TERM_UP			BIT(13)
6063 #define PADCFG1_TERM_SHIFT		10
61
-#define PADCFG1_TERM_MASK		(7 << PADCFG1_TERM_SHIFT)
62
-#define PADCFG1_TERM_20K		4
63
-#define PADCFG1_TERM_2K			3
64
-#define PADCFG1_TERM_5K			2
65
-#define PADCFG1_TERM_1K			1
64
+#define PADCFG1_TERM_MASK		GENMASK(12, 10)
65
+#define PADCFG1_TERM_20K		BIT(2)
66
+#define PADCFG1_TERM_5K			BIT(1)
67
+#define PADCFG1_TERM_1K			BIT(0)
68
+#define PADCFG1_TERM_833		(BIT(1) | BIT(0))
6669 
6770 #define PADCFG2				0x008
6871 #define PADCFG2_DEBEN			BIT(0)
6972 #define PADCFG2_DEBOUNCE_SHIFT		1
7073 #define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)
7174 
72
-#define DEBOUNCE_PERIOD			31250 /* ns */
75
+#define DEBOUNCE_PERIOD_NSEC		31250
7376 
7477 struct intel_pad_context {
7578 	u32 padcfg0;
....@@ -79,44 +82,14 @@
7982 
8083 struct intel_community_context {
8184 	u32 *intmask;
82
-};
83
-
84
-struct intel_pinctrl_context {
85
-	struct intel_pad_context *pads;
86
-	struct intel_community_context *communities;
87
-};
88
-
89
-/**
90
- * struct intel_pinctrl - Intel pinctrl private structure
91
- * @dev: Pointer to the device structure
92
- * @lock: Lock to serialize register access
93
- * @pctldesc: Pin controller description
94
- * @pctldev: Pointer to the pin controller device
95
- * @chip: GPIO chip in this pin controller
96
- * @soc: SoC/PCH specific pin configuration data
97
- * @communities: All communities in this pin controller
98
- * @ncommunities: Number of communities in this pin controller
99
- * @context: Configuration saved over system sleep
100
- * @irq: pinctrl/GPIO chip irq number
101
- */
102
-struct intel_pinctrl {
103
-	struct device *dev;
104
-	raw_spinlock_t lock;
105
-	struct pinctrl_desc pctldesc;
106
-	struct pinctrl_dev *pctldev;
107
-	struct gpio_chip chip;
108
-	const struct intel_pinctrl_soc_data *soc;
109
-	struct intel_community *communities;
110
-	size_t ncommunities;
111
-	struct intel_pinctrl_context context;
112
-	int irq;
85
+	u32 *hostown;
11386 };
11487 
11588 #define pin_to_padno(c, p)	((p) - (c)->pin_base)
11689 #define padgroup_offset(g, p)	((p) - (g)->base)
11790 
11891 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
119
-						   unsigned pin)
92
+						   unsigned int pin)
12093 {
12194 	struct intel_community *community;
12295 	int i;
....@@ -134,7 +107,7 @@
134107 
135108 static const struct intel_padgroup *
136109 intel_community_get_padgroup(const struct intel_community *community,
137
-			     unsigned pin)
110
+			     unsigned int pin)
138111 {
139112 	int i;
140113 
....@@ -148,11 +121,11 @@
148121 	return NULL;
149122 }
150123 
151
-static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
152
-				      unsigned reg)
124
+static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
125
+				      unsigned int pin, unsigned int reg)
153126 {
154127 	const struct intel_community *community;
155
-	unsigned padno;
128
+	unsigned int padno;
156129 	size_t nregs;
157130 
158131 	community = intel_get_community(pctrl, pin);
....@@ -162,17 +135,17 @@
162135 	padno = pin_to_padno(community, pin);
163136 	nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
164137 
165
-	if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
138
+	if (reg >= nregs * 4)
166139 		return NULL;
167140 
168141 	return community->pad_regs + reg + padno * nregs * 4;
169142 }
170143 
171
-static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
144
+static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
172145 {
173146 	const struct intel_community *community;
174147 	const struct intel_padgroup *padgrp;
175
-	unsigned gpp, offset, gpp_offset;
148
+	unsigned int gpp, offset, gpp_offset;
176149 	void __iomem *padown;
177150 
178151 	community = intel_get_community(pctrl, pin);
....@@ -193,11 +166,11 @@
193166 	return !(readl(padown) & PADOWN_MASK(gpp_offset));
194167 }
195168 
196
-static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
169
+static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
197170 {
198171 	const struct intel_community *community;
199172 	const struct intel_padgroup *padgrp;
200
-	unsigned offset, gpp_offset;
173
+	unsigned int offset, gpp_offset;
201174 	void __iomem *hostown;
202175 
203176 	community = intel_get_community(pctrl, pin);
....@@ -217,47 +190,71 @@
217190 	return !(readl(hostown) & BIT(gpp_offset));
218191 }
219192 
220
-static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
193
+/**
194
+ * enum - Locking variants of the pad configuration
195
+ *
196
+ * @PAD_UNLOCKED:	pad is fully controlled by the configuration registers
197
+ * @PAD_LOCKED:		pad configuration registers, except TX state, are locked
198
+ * @PAD_LOCKED_TX:	pad configuration TX state is locked
199
+ * @PAD_LOCKED_FULL:	pad configuration registers are locked completely
200
+ *
201
+ * Locking is considered as read-only mode for corresponding registers and
202
+ * their respective fields. That said, TX state bit is locked separately from
203
+ * the main locking scheme.
204
+ */
205
+enum {
206
+	PAD_UNLOCKED	= 0,
207
+	PAD_LOCKED	= 1,
208
+	PAD_LOCKED_TX	= 2,
209
+	PAD_LOCKED_FULL	= PAD_LOCKED | PAD_LOCKED_TX,
210
+};
211
+
212
+static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
221213 {
222214 	struct intel_community *community;
223215 	const struct intel_padgroup *padgrp;
224
-	unsigned offset, gpp_offset;
216
+	unsigned int offset, gpp_offset;
225217 	u32 value;
218
+	int ret = PAD_UNLOCKED;
226219 
227220 	community = intel_get_community(pctrl, pin);
228221 	if (!community)
229
-		return true;
222
+		return PAD_LOCKED_FULL;
230223 	if (!community->padcfglock_offset)
231
-		return false;
224
+		return PAD_UNLOCKED;
232225 
233226 	padgrp = intel_community_get_padgroup(community, pin);
234227 	if (!padgrp)
235
-		return true;
228
+		return PAD_LOCKED_FULL;
236229 
237230 	gpp_offset = padgroup_offset(padgrp, pin);
238231 
239232 	/*
240233 	 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
241234 	 * the pad is considered unlocked. Any other case means that it is
242
-	 * either fully or partially locked and we don't touch it.
235
+	 * either fully or partially locked.
243236 	 */
244
-	offset = community->padcfglock_offset + padgrp->reg_num * 8;
237
+	offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
245238 	value = readl(community->regs + offset);
246239 	if (value & BIT(gpp_offset))
247
-		return true;
240
+		ret |= PAD_LOCKED;
248241 
249242 	offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
250243 	value = readl(community->regs + offset);
251244 	if (value & BIT(gpp_offset))
252
-		return true;
245
+		ret |= PAD_LOCKED_TX;
253246 
254
-	return false;
247
+	return ret;
255248 }
256249 
257
-static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
250
+static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
258251 {
259
-	return intel_pad_owned_by_host(pctrl, pin) &&
260
-		!intel_pad_locked(pctrl, pin);
252
+	return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
253
+}
254
+
255
+static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
256
+{
257
+	return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
261258 }
262259 
263260 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
....@@ -268,15 +265,15 @@
268265 }
269266 
270267 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
271
-				      unsigned group)
268
+				      unsigned int group)
272269 {
273270 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
274271 
275272 	return pctrl->soc->groups[group].name;
276273 }
277274 
278
-static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
279
-			      const unsigned **pins, unsigned *npins)
275
+static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
276
+			      const unsigned int **pins, unsigned int *npins)
280277 {
281278 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
282279 
....@@ -286,12 +283,13 @@
286283 }
287284 
288285 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
289
-			       unsigned pin)
286
+			       unsigned int pin)
290287 {
291288 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292289 	void __iomem *padcfg;
293290 	u32 cfg0, cfg1, mode;
294
-	bool locked, acpi;
291
+	int locked;
292
+	bool acpi;
295293 
296294 	if (!intel_pad_owned_by_host(pctrl, pin)) {
297295 		seq_puts(s, "not available");
....@@ -319,11 +317,16 @@
319317 
320318 	if (locked || acpi) {
321319 		seq_puts(s, " [");
322
-		if (locked) {
320
+		if (locked)
323321 			seq_puts(s, "LOCKED");
324
-			if (acpi)
325
-				seq_puts(s, ", ");
326
-		}
322
+		if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
323
+			seq_puts(s, " tx");
324
+		else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
325
+			seq_puts(s, " full");
326
+
327
+		if (locked && acpi)
328
+			seq_puts(s, ", ");
329
+
327330 		if (acpi)
328331 			seq_puts(s, "ACPI");
329332 		seq_puts(s, "]");
....@@ -345,7 +348,7 @@
345348 }
346349 
347350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
348
-					   unsigned function)
351
+					   unsigned int function)
349352 {
350353 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
351354 
....@@ -353,9 +356,9 @@
353356 }
354357 
355358 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
356
-				     unsigned function,
359
+				     unsigned int function,
357360 				     const char * const **groups,
358
-				     unsigned * const ngroups)
361
+				     unsigned int * const ngroups)
359362 {
360363 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
361364 
....@@ -364,8 +367,8 @@
364367 	return 0;
365368 }
366369 
367
-static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
368
-				unsigned group)
370
+static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
371
+				unsigned int function, unsigned int group)
369372 {
370373 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
371374 	const struct intel_pingroup *grp = &pctrl->soc->groups[group];
....@@ -423,39 +426,58 @@
423426 	writel(value, padcfg0);
424427 }
425428 
429
+static int __intel_gpio_get_gpio_mode(u32 value)
430
+{
431
+	return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
432
+}
433
+
426434 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
427435 {
428
-	return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
436
+	return __intel_gpio_get_gpio_mode(readl(padcfg0));
429437 }
430438 
431439 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
432440 {
433441 	u32 value;
434442 
443
+	value = readl(padcfg0);
444
+
435445 	/* Put the pad into GPIO mode */
436
-	value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
446
+	value &= ~PADCFG0_PMODE_MASK;
447
+	value |= PADCFG0_PMODE_GPIO;
448
+
449
+	/* Disable TX buffer and enable RX (this will be input) */
450
+	value &= ~PADCFG0_GPIORXDIS;
451
+	value |= PADCFG0_GPIOTXDIS;
452
+
437453 	/* Disable SCI/SMI/NMI generation */
438454 	value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
439455 	value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
456
+
440457 	writel(value, padcfg0);
441458 }
442459 
443460 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
444461 				     struct pinctrl_gpio_range *range,
445
-				     unsigned pin)
462
+				     unsigned int pin)
446463 {
447464 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
448465 	void __iomem *padcfg0;
449466 	unsigned long flags;
450467 
468
+	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
469
+
451470 	raw_spin_lock_irqsave(&pctrl->lock, flags);
452471 
453
-	if (!intel_pad_usable(pctrl, pin)) {
472
+	if (!intel_pad_owned_by_host(pctrl, pin)) {
454473 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
455474 		return -EBUSY;
456475 	}
457476 
458
-	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
477
+	if (!intel_pad_is_unlocked(pctrl, pin)) {
478
+		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
479
+		return 0;
480
+	}
459481 
460482 	/*
461483 	 * If pin is already configured in GPIO mode, we assume that
....@@ -470,9 +492,6 @@
470492 
471493 	intel_gpio_set_gpio_mode(padcfg0);
472494 
473
-	/* Disable TX buffer and enable RX (this will be input) */
474
-	__intel_gpio_set_direction(padcfg0, true);
475
-
476495 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
477496 
478497 	return 0;
....@@ -480,17 +499,16 @@
480499 
481500 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
482501 				    struct pinctrl_gpio_range *range,
483
-				    unsigned pin, bool input)
502
+				    unsigned int pin, bool input)
484503 {
485504 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
486505 	void __iomem *padcfg0;
487506 	unsigned long flags;
488507 
489
-	raw_spin_lock_irqsave(&pctrl->lock, flags);
490
-
491508 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
492
-	__intel_gpio_set_direction(padcfg0, input);
493509 
510
+	raw_spin_lock_irqsave(&pctrl->lock, flags);
511
+	__intel_gpio_set_direction(padcfg0, input);
494512 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
495513 
496514 	return 0;
....@@ -505,20 +523,21 @@
505523 	.gpio_set_direction = intel_gpio_set_direction,
506524 };
507525 
508
-static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
509
-			    unsigned long *config)
526
+static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
527
+				 enum pin_config_param param, u32 *arg)
510528 {
511
-	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
512
-	enum pin_config_param param = pinconf_to_config_param(*config);
513529 	const struct intel_community *community;
530
+	void __iomem *padcfg1;
531
+	unsigned long flags;
514532 	u32 value, term;
515
-	u32 arg = 0;
516
-
517
-	if (!intel_pad_owned_by_host(pctrl, pin))
518
-		return -ENOTSUPP;
519533 
520534 	community = intel_get_community(pctrl, pin);
521
-	value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
535
+	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
536
+
537
+	raw_spin_lock_irqsave(&pctrl->lock, flags);
538
+	value = readl(padcfg1);
539
+	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
540
+
522541 	term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
523542 
524543 	switch (param) {
....@@ -532,17 +551,17 @@
532551 			return -EINVAL;
533552 
534553 		switch (term) {
535
-		case PADCFG1_TERM_1K:
536
-			arg = 1000;
554
+		case PADCFG1_TERM_833:
555
+			*arg = 833;
537556 			break;
538
-		case PADCFG1_TERM_2K:
539
-			arg = 2000;
557
+		case PADCFG1_TERM_1K:
558
+			*arg = 1000;
540559 			break;
541560 		case PADCFG1_TERM_5K:
542
-			arg = 5000;
561
+			*arg = 5000;
543562 			break;
544563 		case PADCFG1_TERM_20K:
545
-			arg = 20000;
564
+			*arg = 20000;
546565 			break;
547566 		}
548567 
....@@ -553,38 +572,82 @@
553572 			return -EINVAL;
554573 
555574 		switch (term) {
575
+		case PADCFG1_TERM_833:
576
+			if (!(community->features & PINCTRL_FEATURE_1K_PD))
577
+				return -EINVAL;
578
+			*arg = 833;
579
+			break;
556580 		case PADCFG1_TERM_1K:
557581 			if (!(community->features & PINCTRL_FEATURE_1K_PD))
558582 				return -EINVAL;
559
-			arg = 1000;
583
+			*arg = 1000;
560584 			break;
561585 		case PADCFG1_TERM_5K:
562
-			arg = 5000;
586
+			*arg = 5000;
563587 			break;
564588 		case PADCFG1_TERM_20K:
565
-			arg = 20000;
589
+			*arg = 20000;
566590 			break;
567591 		}
568592 
569593 		break;
570594 
571
-	case PIN_CONFIG_INPUT_DEBOUNCE: {
572
-		void __iomem *padcfg2;
573
-		u32 v;
574
-
575
-		padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
576
-		if (!padcfg2)
577
-			return -ENOTSUPP;
578
-
579
-		v = readl(padcfg2);
580
-		if (!(v & PADCFG2_DEBEN))
581
-			return -EINVAL;
582
-
583
-		v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
584
-		arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
585
-
586
-		break;
595
+	default:
596
+		return -EINVAL;
587597 	}
598
+
599
+	return 0;
600
+}
601
+
602
+static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
603
+				     enum pin_config_param param, u32 *arg)
604
+{
605
+	void __iomem *padcfg2;
606
+	unsigned long flags;
607
+	unsigned long v;
608
+	u32 value2;
609
+
610
+	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
611
+	if (!padcfg2)
612
+		return -ENOTSUPP;
613
+
614
+	raw_spin_lock_irqsave(&pctrl->lock, flags);
615
+	value2 = readl(padcfg2);
616
+	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
617
+	if (!(value2 & PADCFG2_DEBEN))
618
+		return -EINVAL;
619
+
620
+	v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
621
+	*arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
622
+
623
+	return 0;
624
+}
625
+
626
+static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
627
+			    unsigned long *config)
628
+{
629
+	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
630
+	enum pin_config_param param = pinconf_to_config_param(*config);
631
+	u32 arg = 0;
632
+	int ret;
633
+
634
+	if (!intel_pad_owned_by_host(pctrl, pin))
635
+		return -ENOTSUPP;
636
+
637
+	switch (param) {
638
+	case PIN_CONFIG_BIAS_DISABLE:
639
+	case PIN_CONFIG_BIAS_PULL_UP:
640
+	case PIN_CONFIG_BIAS_PULL_DOWN:
641
+		ret = intel_config_get_pull(pctrl, pin, param, &arg);
642
+		if (ret)
643
+			return ret;
644
+		break;
645
+
646
+	case PIN_CONFIG_INPUT_DEBOUNCE:
647
+		ret = intel_config_get_debounce(pctrl, pin, param, &arg);
648
+		if (ret)
649
+			return ret;
650
+		break;
588651 
589652 	default:
590653 		return -ENOTSUPP;
....@@ -594,21 +657,22 @@
594657 	return 0;
595658 }
596659 
597
-static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
660
+static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
598661 				 unsigned long config)
599662 {
600
-	unsigned param = pinconf_to_config_param(config);
601
-	unsigned arg = pinconf_to_config_argument(config);
663
+	unsigned int param = pinconf_to_config_param(config);
664
+	unsigned int arg = pinconf_to_config_argument(config);
602665 	const struct intel_community *community;
603666 	void __iomem *padcfg1;
604667 	unsigned long flags;
605668 	int ret = 0;
606669 	u32 value;
607670 
608
-	raw_spin_lock_irqsave(&pctrl->lock, flags);
609
-
610671 	community = intel_get_community(pctrl, pin);
611672 	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
673
+
674
+	raw_spin_lock_irqsave(&pctrl->lock, flags);
675
+
612676 	value = readl(padcfg1);
613677 
614678 	switch (param) {
....@@ -632,11 +696,11 @@
632696 		case 5000:
633697 			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
634698 			break;
635
-		case 2000:
636
-			value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
637
-			break;
638699 		case 1000:
639700 			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
701
+			break;
702
+		case 833:
703
+			value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
640704 			break;
641705 		default:
642706 			ret = -EINVAL;
....@@ -665,6 +729,13 @@
665729 			}
666730 			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
667731 			break;
732
+		case 833:
733
+			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
734
+				ret = -EINVAL;
735
+				break;
736
+			}
737
+			value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
738
+			break;
668739 		default:
669740 			ret = -EINVAL;
670741 		}
....@@ -680,13 +751,12 @@
680751 	return ret;
681752 }
682753 
683
-static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
684
-				     unsigned debounce)
754
+static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
755
+				     unsigned int pin, unsigned int debounce)
685756 {
686757 	void __iomem *padcfg0, *padcfg2;
687758 	unsigned long flags;
688759 	u32 value0, value2;
689
-	int ret = 0;
690760 
691761 	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
692762 	if (!padcfg2)
....@@ -706,29 +776,28 @@
706776 	if (debounce) {
707777 		unsigned long v;
708778 
709
-		v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
779
+		v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
710780 		if (v < 3 || v > 15) {
711
-			ret = -EINVAL;
712
-			goto exit_unlock;
713
-		} else {
714
-			/* Enable glitch filter and debouncer */
715
-			value0 |= PADCFG0_PREGFRXSEL;
716
-			value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
717
-			value2 |= PADCFG2_DEBEN;
781
+			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
782
+			return -EINVAL;
718783 		}
784
+
785
+		/* Enable glitch filter and debouncer */
786
+		value0 |= PADCFG0_PREGFRXSEL;
787
+		value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
788
+		value2 |= PADCFG2_DEBEN;
719789 	}
720790 
721791 	writel(value0, padcfg0);
722792 	writel(value2, padcfg2);
723793 
724
-exit_unlock:
725794 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
726795 
727
-	return ret;
796
+	return 0;
728797 }
729798 
730
-static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
731
-			  unsigned long *configs, unsigned nconfigs)
799
+static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
800
+			  unsigned long *configs, unsigned int nconfigs)
732801 {
733802 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
734803 	int i, ret;
....@@ -778,14 +847,14 @@
778847  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
779848  * @pctrl: Pinctrl structure
780849  * @offset: GPIO offset from gpiolib
781
- * @commmunity: Community is filled here if not %NULL
850
+ * @community: Community is filled here if not %NULL
782851  * @padgrp: Pad group is filled here if not %NULL
783852  *
784853  * When coming through gpiolib irqchip, the GPIO offset is not
785854  * automatically translated to pinctrl pin number. This function can be
786855  * used to find out the corresponding pinctrl pin.
787856  */
788
-static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
857
+static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
789858 			     const struct intel_community **community,
790859 			     const struct intel_padgroup **padgrp)
791860 {
....@@ -798,7 +867,7 @@
798867 		for (j = 0; j < comm->ngpps; j++) {
799868 			const struct intel_padgroup *pgrp = &comm->gpps[j];
800869 
801
-			if (pgrp->gpio_base < 0)
870
+			if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
802871 				continue;
803872 
804873 			if (offset >= pgrp->gpio_base &&
....@@ -819,7 +888,30 @@
819888 	return -EINVAL;
820889 }
821890 
822
-static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
891
+/**
892
+ * intel_pin_to_gpio() - Translate from pin number to GPIO offset
893
+ * @pctrl: Pinctrl structure
894
+ * @pin: pin number
895
+ *
896
+ * Translate the pin number of pinctrl to GPIO offset
897
+ */
898
+static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
899
+{
900
+	const struct intel_community *community;
901
+	const struct intel_padgroup *padgrp;
902
+
903
+	community = intel_get_community(pctrl, pin);
904
+	if (!community)
905
+		return -EINVAL;
906
+
907
+	padgrp = intel_community_get_padgroup(community, pin);
908
+	if (!padgrp)
909
+		return -EINVAL;
910
+
911
+	return pin - padgrp->base + padgrp->gpio_base;
912
+}
913
+
914
+static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
823915 {
824916 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
825917 	void __iomem *reg;
....@@ -841,7 +933,8 @@
841933 	return !!(padcfg0 & PADCFG0_GPIORXSTATE);
842934 }
843935 
844
-static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
936
+static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
937
+			   int value)
845938 {
846939 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
847940 	unsigned long flags;
....@@ -870,6 +963,7 @@
870963 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
871964 {
872965 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
966
+	unsigned long flags;
873967 	void __iomem *reg;
874968 	u32 padcfg0;
875969 	int pin;
....@@ -882,20 +976,24 @@
882976 	if (!reg)
883977 		return -EINVAL;
884978 
979
+	raw_spin_lock_irqsave(&pctrl->lock, flags);
885980 	padcfg0 = readl(reg);
886
-
981
+	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
887982 	if (padcfg0 & PADCFG0_PMODE_MASK)
888983 		return -EINVAL;
889984 
890
-	return !!(padcfg0 & PADCFG0_GPIOTXDIS);
985
+	if (padcfg0 & PADCFG0_GPIOTXDIS)
986
+		return GPIO_LINE_DIRECTION_IN;
987
+
988
+	return GPIO_LINE_DIRECTION_OUT;
891989 }
892990 
893
-static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
991
+static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
894992 {
895993 	return pinctrl_gpio_direction_input(chip->base + offset);
896994 }
897995 
898
-static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
996
+static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
899997 				       int value)
900998 {
901999 	intel_gpio_set(chip, offset, value);
....@@ -924,7 +1022,7 @@
9241022 
9251023 	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
9261024 	if (pin >= 0) {
927
-		unsigned gpp, gpp_offset, is_offset;
1025
+		unsigned int gpp, gpp_offset, is_offset;
9281026 
9291027 		gpp = padgrp->reg_num;
9301028 		gpp_offset = padgroup_offset(padgrp, pin);
....@@ -933,35 +1031,6 @@
9331031 		raw_spin_lock(&pctrl->lock);
9341032 		writel(BIT(gpp_offset), community->regs + is_offset);
9351033 		raw_spin_unlock(&pctrl->lock);
936
-	}
937
-}
938
-
939
-static void intel_gpio_irq_enable(struct irq_data *d)
940
-{
941
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
942
-	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
943
-	const struct intel_community *community;
944
-	const struct intel_padgroup *padgrp;
945
-	int pin;
946
-
947
-	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
948
-	if (pin >= 0) {
949
-		unsigned gpp, gpp_offset, is_offset;
950
-		unsigned long flags;
951
-		u32 value;
952
-
953
-		gpp = padgrp->reg_num;
954
-		gpp_offset = padgroup_offset(padgrp, pin);
955
-		is_offset = community->is_offset + gpp * 4;
956
-
957
-		raw_spin_lock_irqsave(&pctrl->lock, flags);
958
-		/* Clear interrupt status first to avoid unexpected interrupt */
959
-		writel(BIT(gpp_offset), community->regs + is_offset);
960
-
961
-		value = readl(community->regs + community->ie_offset + gpp * 4);
962
-		value |= BIT(gpp_offset);
963
-		writel(value, community->regs + community->ie_offset + gpp * 4);
964
-		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
9651034 	}
9661035 }
9671036 
....@@ -975,17 +1044,22 @@
9751044 
9761045 	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
9771046 	if (pin >= 0) {
978
-		unsigned gpp, gpp_offset;
1047
+		unsigned int gpp, gpp_offset;
9791048 		unsigned long flags;
980
-		void __iomem *reg;
1049
+		void __iomem *reg, *is;
9811050 		u32 value;
9821051 
9831052 		gpp = padgrp->reg_num;
9841053 		gpp_offset = padgroup_offset(padgrp, pin);
9851054 
9861055 		reg = community->regs + community->ie_offset + gpp * 4;
1056
+		is = community->regs + community->is_offset + gpp * 4;
9871057 
9881058 		raw_spin_lock_irqsave(&pctrl->lock, flags);
1059
+
1060
+		/* Clear interrupt status first to avoid unexpected interrupt */
1061
+		writel(BIT(gpp_offset), is);
1062
+
9891063 		value = readl(reg);
9901064 		if (mask)
9911065 			value &= ~BIT(gpp_offset);
....@@ -1006,11 +1080,11 @@
10061080 	intel_gpio_irq_mask_unmask(d, false);
10071081 }
10081082 
1009
-static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
1083
+static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
10101084 {
10111085 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
10121086 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1013
-	unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1087
+	unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
10141088 	unsigned long flags;
10151089 	void __iomem *reg;
10161090 	u32 value;
....@@ -1067,7 +1141,7 @@
10671141 {
10681142 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
10691143 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1070
-	unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1144
+	unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
10711145 
10721146 	if (on)
10731147 		enable_irq_wake(pctrl->irq);
....@@ -1078,34 +1152,39 @@
10781152 	return 0;
10791153 }
10801154 
1081
-static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1082
-	const struct intel_community *community)
1155
+static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1156
+					    const struct intel_community *community)
10831157 {
10841158 	struct gpio_chip *gc = &pctrl->chip;
1085
-	irqreturn_t ret = IRQ_NONE;
1086
-	int gpp;
1159
+	unsigned int gpp;
1160
+	int ret = 0;
10871161 
10881162 	for (gpp = 0; gpp < community->ngpps; gpp++) {
10891163 		const struct intel_padgroup *padgrp = &community->gpps[gpp];
10901164 		unsigned long pending, enabled, gpp_offset;
1165
+		unsigned long flags;
1166
+
1167
+		raw_spin_lock_irqsave(&pctrl->lock, flags);
10911168 
10921169 		pending = readl(community->regs + community->is_offset +
10931170 				padgrp->reg_num * 4);
10941171 		enabled = readl(community->regs + community->ie_offset +
10951172 				padgrp->reg_num * 4);
10961173 
1174
+		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1175
+
10971176 		/* Only interrupts that are enabled */
10981177 		pending &= enabled;
10991178 
11001179 		for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1101
-			unsigned irq;
1180
+			unsigned int irq;
11021181 
11031182 			irq = irq_find_mapping(gc->irq.domain,
11041183 					       padgrp->gpio_base + gpp_offset);
11051184 			generic_handle_irq(irq);
1106
-
1107
-			ret |= IRQ_HANDLED;
11081185 		}
1186
+
1187
+		ret += pending ? 1 : 0;
11091188 	}
11101189 
11111190 	return ret;
....@@ -1115,38 +1194,60 @@
11151194 {
11161195 	const struct intel_community *community;
11171196 	struct intel_pinctrl *pctrl = data;
1118
-	irqreturn_t ret = IRQ_NONE;
1119
-	int i;
1197
+	unsigned int i;
1198
+	int ret = 0;
11201199 
11211200 	/* Need to check all communities for pending interrupts */
11221201 	for (i = 0; i < pctrl->ncommunities; i++) {
11231202 		community = &pctrl->communities[i];
1124
-		ret |= intel_gpio_community_irq_handler(pctrl, community);
1203
+		ret += intel_gpio_community_irq_handler(pctrl, community);
11251204 	}
11261205 
1127
-	return ret;
1206
+	return IRQ_RETVAL(ret);
11281207 }
11291208 
1130
-static struct irq_chip intel_gpio_irqchip = {
1131
-	.name = "intel-gpio",
1132
-	.irq_enable = intel_gpio_irq_enable,
1133
-	.irq_ack = intel_gpio_irq_ack,
1134
-	.irq_mask = intel_gpio_irq_mask,
1135
-	.irq_unmask = intel_gpio_irq_unmask,
1136
-	.irq_set_type = intel_gpio_irq_type,
1137
-	.irq_set_wake = intel_gpio_irq_wake,
1138
-	.flags = IRQCHIP_MASK_ON_SUSPEND,
1139
-};
1209
+static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1210
+{
1211
+	int i;
11401212 
1141
-static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1142
-				     const struct intel_community *community)
1213
+	for (i = 0; i < pctrl->ncommunities; i++) {
1214
+		const struct intel_community *community;
1215
+		void __iomem *base;
1216
+		unsigned int gpp;
1217
+
1218
+		community = &pctrl->communities[i];
1219
+		base = community->regs;
1220
+
1221
+		for (gpp = 0; gpp < community->ngpps; gpp++) {
1222
+			/* Mask and clear all interrupts */
1223
+			writel(0, base + community->ie_offset + gpp * 4);
1224
+			writel(0xffff, base + community->is_offset + gpp * 4);
1225
+		}
1226
+	}
1227
+}
1228
+
1229
+static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1230
+{
1231
+	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1232
+
1233
+	/*
1234
+	 * Make sure the interrupt lines are in a proper state before
1235
+	 * further configuration.
1236
+	 */
1237
+	intel_gpio_irq_init(pctrl);
1238
+
1239
+	return 0;
1240
+}
1241
+
1242
+static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1243
+				const struct intel_community *community)
11431244 {
11441245 	int ret = 0, i;
11451246 
11461247 	for (i = 0; i < community->ngpps; i++) {
11471248 		const struct intel_padgroup *gpp = &community->gpps[i];
11481249 
1149
-		if (gpp->gpio_base < 0)
1250
+		if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
11501251 			continue;
11511252 
11521253 		ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
....@@ -1159,10 +1260,28 @@
11591260 	return ret;
11601261 }
11611262 
1162
-static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1263
+static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1264
+{
1265
+	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1266
+	int ret, i;
1267
+
1268
+	for (i = 0; i < pctrl->ncommunities; i++) {
1269
+		struct intel_community *community = &pctrl->communities[i];
1270
+
1271
+		ret = intel_gpio_add_community_ranges(pctrl, community);
1272
+		if (ret) {
1273
+			dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1274
+			return ret;
1275
+		}
1276
+	}
1277
+
1278
+	return 0;
1279
+}
1280
+
1281
+static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
11631282 {
11641283 	const struct intel_community *community;
1165
-	unsigned ngpio = 0;
1284
+	unsigned int ngpio = 0;
11661285 	int i, j;
11671286 
11681287 	for (i = 0; i < pctrl->ncommunities; i++) {
....@@ -1170,7 +1289,7 @@
11701289 		for (j = 0; j < community->ngpps; j++) {
11711290 			const struct intel_padgroup *gpp = &community->gpps[j];
11721291 
1173
-			if (gpp->gpio_base < 0)
1292
+			if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
11741293 				continue;
11751294 
11761295 			if (gpp->gpio_base + gpp->size > ngpio)
....@@ -1183,36 +1302,31 @@
11831302 
11841303 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
11851304 {
1186
-	int ret, i;
1305
+	int ret;
1306
+	struct gpio_irq_chip *girq;
11871307 
11881308 	pctrl->chip = intel_gpio_chip;
11891309 
1310
+	/* Setup GPIO chip */
11901311 	pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
11911312 	pctrl->chip.label = dev_name(pctrl->dev);
11921313 	pctrl->chip.parent = pctrl->dev;
11931314 	pctrl->chip.base = -1;
1315
+	pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
11941316 	pctrl->irq = irq;
11951317 
1196
-	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1197
-	if (ret) {
1198
-		dev_err(pctrl->dev, "failed to register gpiochip\n");
1199
-		return ret;
1200
-	}
1201
-
1202
-	for (i = 0; i < pctrl->ncommunities; i++) {
1203
-		struct intel_community *community = &pctrl->communities[i];
1204
-
1205
-		ret = intel_gpio_add_pin_ranges(pctrl, community);
1206
-		if (ret) {
1207
-			dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1208
-			return ret;
1209
-		}
1210
-	}
1318
+	/* Setup IRQ chip */
1319
+	pctrl->irqchip.name = dev_name(pctrl->dev);
1320
+	pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1321
+	pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1322
+	pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1323
+	pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1324
+	pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1325
+	pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
12111326 
12121327 	/*
1213
-	 * We need to request the interrupt here (instead of providing chip
1214
-	 * to the irq directly) because on some platforms several GPIO
1215
-	 * controllers share the same interrupt line.
1328
+	 * On some platforms several GPIO controllers share the same interrupt
1329
+	 * line.
12161330 	 */
12171331 	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
12181332 			       IRQF_SHARED | IRQF_NO_THREAD,
....@@ -1222,15 +1336,21 @@
12221336 		return ret;
12231337 	}
12241338 
1225
-	ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1226
-				   handle_bad_irq, IRQ_TYPE_NONE);
1339
+	girq = &pctrl->chip.irq;
1340
+	girq->chip = &pctrl->irqchip;
1341
+	/* This will let us handle the IRQ in the driver */
1342
+	girq->parent_handler = NULL;
1343
+	girq->num_parents = 0;
1344
+	girq->default_type = IRQ_TYPE_NONE;
1345
+	girq->handler = handle_bad_irq;
1346
+	girq->init_hw = intel_gpio_irq_init_hw;
1347
+
1348
+	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
12271349 	if (ret) {
1228
-		dev_err(pctrl->dev, "failed to add irqchip\n");
1350
+		dev_err(pctrl->dev, "failed to register gpiochip\n");
12291351 		return ret;
12301352 	}
12311353 
1232
-	gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1233
-				     NULL);
12341354 	return 0;
12351355 }
12361356 
....@@ -1238,8 +1358,8 @@
12381358 				       struct intel_community *community)
12391359 {
12401360 	struct intel_padgroup *gpps;
1241
-	unsigned npins = community->npins;
1242
-	unsigned padown_num = 0;
1361
+	unsigned int npins = community->npins;
1362
+	unsigned int padown_num = 0;
12431363 	size_t ngpps, i;
12441364 
12451365 	if (community->gpps)
....@@ -1255,7 +1375,7 @@
12551375 		if (community->gpps) {
12561376 			gpps[i] = community->gpps[i];
12571377 		} else {
1258
-			unsigned gpp_size = community->gpp_size;
1378
+			unsigned int gpp_size = community->gpp_size;
12591379 
12601380 			gpps[i].reg_num = i;
12611381 			gpps[i].base = community->pin_base + i * gpp_size;
....@@ -1266,8 +1386,18 @@
12661386 		if (gpps[i].size > 32)
12671387 			return -EINVAL;
12681388 
1269
-		if (!gpps[i].gpio_base)
1270
-			gpps[i].gpio_base = gpps[i].base;
1389
+		/* Special treatment for GPIO base */
1390
+		switch (gpps[i].gpio_base) {
1391
+			case INTEL_GPIO_BASE_MATCH:
1392
+				gpps[i].gpio_base = gpps[i].base;
1393
+				break;
1394
+			case INTEL_GPIO_BASE_ZERO:
1395
+				gpps[i].gpio_base = 0;
1396
+				break;
1397
+			case INTEL_GPIO_BASE_NOMAP:
1398
+			default:
1399
+				break;
1400
+		}
12711401 
12721402 		gpps[i].padown_num = padown_num;
12731403 
....@@ -1307,7 +1437,7 @@
13071437 
13081438 	for (i = 0; i < pctrl->ncommunities; i++) {
13091439 		struct intel_community *community = &pctrl->communities[i];
1310
-		u32 *intmask;
1440
+		u32 *intmask, *hostown;
13111441 
13121442 		intmask = devm_kcalloc(pctrl->dev, community->ngpps,
13131443 				       sizeof(*intmask), GFP_KERNEL);
....@@ -1315,6 +1445,13 @@
13151445 			return -ENOMEM;
13161446 
13171447 		communities[i].intmask = intmask;
1448
+
1449
+		hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1450
+				       sizeof(*hostown), GFP_KERNEL);
1451
+		if (!hostown)
1452
+			return -ENOMEM;
1453
+
1454
+		communities[i].hostown = hostown;
13181455 	}
13191456 
13201457 	pctrl->context.pads = pads;
....@@ -1324,14 +1461,11 @@
13241461 	return 0;
13251462 }
13261463 
1327
-int intel_pinctrl_probe(struct platform_device *pdev,
1328
-			const struct intel_pinctrl_soc_data *soc_data)
1464
+static int intel_pinctrl_probe(struct platform_device *pdev,
1465
+			       const struct intel_pinctrl_soc_data *soc_data)
13291466 {
13301467 	struct intel_pinctrl *pctrl;
13311468 	int i, ret, irq;
1332
-
1333
-	if (!soc_data)
1334
-		return -EINVAL;
13351469 
13361470 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
13371471 	if (!pctrl)
....@@ -1353,15 +1487,12 @@
13531487 
13541488 	for (i = 0; i < pctrl->ncommunities; i++) {
13551489 		struct intel_community *community = &pctrl->communities[i];
1356
-		struct resource *res;
13571490 		void __iomem *regs;
13581491 		u32 padbar;
13591492 
13601493 		*community = pctrl->soc->communities[i];
13611494 
1362
-		res = platform_get_resource(pdev, IORESOURCE_MEM,
1363
-					    community->barno);
1364
-		regs = devm_ioremap_resource(&pdev->dev, res);
1495
+		regs = devm_platform_ioremap_resource(pdev, community->barno);
13651496 		if (IS_ERR(regs))
13661497 			return PTR_ERR(regs);
13671498 
....@@ -1385,19 +1516,14 @@
13851516 		community->regs = regs;
13861517 		community->pad_regs = regs + padbar;
13871518 
1388
-		if (!community->is_offset)
1389
-			community->is_offset = GPI_IS;
1390
-
13911519 		ret = intel_pinctrl_add_padgroups(pctrl, community);
13921520 		if (ret)
13931521 			return ret;
13941522 	}
13951523 
13961524 	irq = platform_get_irq(pdev, 0);
1397
-	if (irq < 0) {
1398
-		dev_err(&pdev->dev, "failed to get interrupt number\n");
1525
+	if (irq < 0)
13991526 		return irq;
1400
-	}
14011527 
14021528 	ret = intel_pinctrl_pm_init(pctrl);
14031529 	if (ret)
....@@ -1423,12 +1549,73 @@
14231549 
14241550 	return 0;
14251551 }
1426
-EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1552
+
1553
+int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1554
+{
1555
+	const struct intel_pinctrl_soc_data *data;
1556
+
1557
+	data = device_get_match_data(&pdev->dev);
1558
+	if (!data)
1559
+		return -ENODATA;
1560
+
1561
+	return intel_pinctrl_probe(pdev, data);
1562
+}
1563
+EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1564
+
1565
+int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1566
+{
1567
+	const struct intel_pinctrl_soc_data *data;
1568
+
1569
+	data = intel_pinctrl_get_soc_data(pdev);
1570
+	if (IS_ERR(data))
1571
+		return PTR_ERR(data);
1572
+
1573
+	return intel_pinctrl_probe(pdev, data);
1574
+}
1575
+EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1576
+
1577
+const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1578
+{
1579
+	const struct intel_pinctrl_soc_data * const *table;
1580
+	const struct intel_pinctrl_soc_data *data = NULL;
1581
+
1582
+	table = device_get_match_data(&pdev->dev);
1583
+	if (table) {
1584
+		struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
1585
+		unsigned int i;
1586
+
1587
+		for (i = 0; table[i]; i++) {
1588
+			if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1589
+				data = table[i];
1590
+				break;
1591
+			}
1592
+		}
1593
+	} else {
1594
+		const struct platform_device_id *id;
1595
+
1596
+		id = platform_get_device_id(pdev);
1597
+		if (!id)
1598
+			return ERR_PTR(-ENODEV);
1599
+
1600
+		table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1601
+		data = table[pdev->id];
1602
+	}
1603
+
1604
+	return data ?: ERR_PTR(-ENODATA);
1605
+}
1606
+EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
14271607 
14281608 #ifdef CONFIG_PM_SLEEP
1429
-static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1609
+static bool __intel_gpio_is_direct_irq(u32 value)
1610
+{
1611
+	return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1612
+	       (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1613
+}
1614
+
1615
+static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
14301616 {
14311617 	const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1618
+	u32 value;
14321619 
14331620 	if (!pd || !intel_pad_usable(pctrl, pin))
14341621 		return false;
....@@ -1440,16 +1627,33 @@
14401627 	 * them alone.
14411628 	 */
14421629 	if (pd->mux_owner || pd->gpio_owner ||
1443
-	    gpiochip_line_is_irq(&pctrl->chip, pin))
1630
+	    gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1631
+		return true;
1632
+
1633
+	/*
1634
+	 * The firmware on some systems may configure GPIO pins to be
1635
+	 * an interrupt source in so called "direct IRQ" mode. In such
1636
+	 * cases the GPIO controller driver has no idea if those pins
1637
+	 * are being used or not. At the same time, there is a known bug
1638
+	 * in the firmwares that don't restore the pin settings correctly
1639
+	 * after suspend, i.e. by an unknown reason the Rx value becomes
1640
+	 * inverted.
1641
+	 *
1642
+	 * Hence, let's save and restore the pins that are configured
1643
+	 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1644
+	 *
1645
+	 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1646
+	 */
1647
+	value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1648
+	if (__intel_gpio_is_direct_irq(value))
14441649 		return true;
14451650 
14461651 	return false;
14471652 }
14481653 
1449
-int intel_pinctrl_suspend(struct device *dev)
1654
+int intel_pinctrl_suspend_noirq(struct device *dev)
14501655 {
1451
-	struct platform_device *pdev = to_platform_device(dev);
1452
-	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1656
+	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
14531657 	struct intel_community_context *communities;
14541658 	struct intel_pad_context *pads;
14551659 	int i;
....@@ -1477,41 +1681,89 @@
14771681 	for (i = 0; i < pctrl->ncommunities; i++) {
14781682 		struct intel_community *community = &pctrl->communities[i];
14791683 		void __iomem *base;
1480
-		unsigned gpp;
1684
+		unsigned int gpp;
14811685 
14821686 		base = community->regs + community->ie_offset;
14831687 		for (gpp = 0; gpp < community->ngpps; gpp++)
14841688 			communities[i].intmask[gpp] = readl(base + gpp * 4);
1689
+
1690
+		base = community->regs + community->hostown_offset;
1691
+		for (gpp = 0; gpp < community->ngpps; gpp++)
1692
+			communities[i].hostown[gpp] = readl(base + gpp * 4);
14851693 	}
14861694 
14871695 	return 0;
14881696 }
1489
-EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1697
+EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
14901698 
1491
-static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1699
+static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
14921700 {
1493
-	size_t i;
1701
+	u32 curr, updated;
14941702 
1495
-	for (i = 0; i < pctrl->ncommunities; i++) {
1496
-		const struct intel_community *community;
1497
-		void __iomem *base;
1498
-		unsigned gpp;
1703
+	curr = readl(reg);
14991704 
1500
-		community = &pctrl->communities[i];
1501
-		base = community->regs;
1705
+	updated = (curr & ~mask) | (value & mask);
1706
+	if (curr == updated)
1707
+		return false;
15021708 
1503
-		for (gpp = 0; gpp < community->ngpps; gpp++) {
1504
-			/* Mask and clear all interrupts */
1505
-			writel(0, base + community->ie_offset + gpp * 4);
1506
-			writel(0xffff, base + community->is_offset + gpp * 4);
1507
-		}
1508
-	}
1709
+	writel(updated, reg);
1710
+	return true;
15091711 }
15101712 
1511
-int intel_pinctrl_resume(struct device *dev)
1713
+static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1714
+				  void __iomem *base, unsigned int gpp, u32 saved)
15121715 {
1513
-	struct platform_device *pdev = to_platform_device(dev);
1514
-	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1716
+	const struct intel_community *community = &pctrl->communities[c];
1717
+	const struct intel_padgroup *padgrp = &community->gpps[gpp];
1718
+	struct device *dev = pctrl->dev;
1719
+	const char *dummy;
1720
+	u32 requested = 0;
1721
+	unsigned int i;
1722
+
1723
+	if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1724
+		return;
1725
+
1726
+	for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1727
+		requested |= BIT(i);
1728
+
1729
+	if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1730
+		return;
1731
+
1732
+	dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1733
+}
1734
+
1735
+static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1736
+				  void __iomem *base, unsigned int gpp, u32 saved)
1737
+{
1738
+	struct device *dev = pctrl->dev;
1739
+
1740
+	if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1741
+		return;
1742
+
1743
+	dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1744
+}
1745
+
1746
+static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1747
+				 unsigned int reg, u32 saved)
1748
+{
1749
+	u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1750
+	unsigned int n = reg / sizeof(u32);
1751
+	struct device *dev = pctrl->dev;
1752
+	void __iomem *padcfg;
1753
+
1754
+	padcfg = intel_get_padcfg(pctrl, pin, reg);
1755
+	if (!padcfg)
1756
+		return;
1757
+
1758
+	if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1759
+		return;
1760
+
1761
+	dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1762
+}
1763
+
1764
+int intel_pinctrl_resume_noirq(struct device *dev)
1765
+{
1766
+	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
15151767 	const struct intel_community_context *communities;
15161768 	const struct intel_pad_context *pads;
15171769 	int i;
....@@ -1522,56 +1774,38 @@
15221774 	pads = pctrl->context.pads;
15231775 	for (i = 0; i < pctrl->soc->npins; i++) {
15241776 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1525
-		void __iomem *padcfg;
1526
-		u32 val;
15271777 
1528
-		if (!intel_pinctrl_should_save(pctrl, desc->number))
1778
+		if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1779
+		      /*
1780
+		       * If the firmware mangled the register contents too much,
1781
+		       * check the saved value for the Direct IRQ mode.
1782
+		       */
1783
+		      __intel_gpio_is_direct_irq(pads[i].padcfg0)))
15291784 			continue;
15301785 
1531
-		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1532
-		val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1533
-		if (val != pads[i].padcfg0) {
1534
-			writel(pads[i].padcfg0, padcfg);
1535
-			dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1536
-				desc->number, readl(padcfg));
1537
-		}
1538
-
1539
-		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1540
-		val = readl(padcfg);
1541
-		if (val != pads[i].padcfg1) {
1542
-			writel(pads[i].padcfg1, padcfg);
1543
-			dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1544
-				desc->number, readl(padcfg));
1545
-		}
1546
-
1547
-		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1548
-		if (padcfg) {
1549
-			val = readl(padcfg);
1550
-			if (val != pads[i].padcfg2) {
1551
-				writel(pads[i].padcfg2, padcfg);
1552
-				dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1553
-					desc->number, readl(padcfg));
1554
-			}
1555
-		}
1786
+		intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1787
+		intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1788
+		intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
15561789 	}
15571790 
15581791 	communities = pctrl->context.communities;
15591792 	for (i = 0; i < pctrl->ncommunities; i++) {
15601793 		struct intel_community *community = &pctrl->communities[i];
15611794 		void __iomem *base;
1562
-		unsigned gpp;
1795
+		unsigned int gpp;
15631796 
15641797 		base = community->regs + community->ie_offset;
1565
-		for (gpp = 0; gpp < community->ngpps; gpp++) {
1566
-			writel(communities[i].intmask[gpp], base + gpp * 4);
1567
-			dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1568
-				readl(base + gpp * 4));
1569
-		}
1798
+		for (gpp = 0; gpp < community->ngpps; gpp++)
1799
+			intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1800
+
1801
+		base = community->regs + community->hostown_offset;
1802
+		for (gpp = 0; gpp < community->ngpps; gpp++)
1803
+			intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
15701804 	}
15711805 
15721806 	return 0;
15731807 }
1574
-EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1808
+EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
15751809 #endif
15761810 
15771811 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");