| .. | .. |
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| 6 | 6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
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| 7 | 7 | */ |
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| 8 | 8 | |
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| 9 | | -#include <linux/acpi.h> |
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| 9 | +#include <linux/mod_devicetable.h> |
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| 10 | 10 | #include <linux/module.h> |
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| 11 | 11 | #include <linux/platform_device.h> |
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| 12 | | -#include <linux/pm.h> |
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| 12 | + |
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| 13 | 13 | #include <linux/pinctrl/pinctrl.h> |
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| 14 | 14 | |
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| 15 | 15 | #include "pinctrl-intel.h" |
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| 16 | 16 | |
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| 17 | 17 | #define BXT_PAD_OWN 0x020 |
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| 18 | | -#define BXT_HOSTSW_OWN 0x080 |
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| 19 | 18 | #define BXT_PADCFGLOCK 0x060 |
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| 19 | +#define BXT_HOSTSW_OWN 0x080 |
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| 20 | +#define BXT_GPI_IS 0x100 |
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| 20 | 21 | #define BXT_GPI_IE 0x110 |
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| 21 | 22 | |
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| 22 | 23 | #define BXT_COMMUNITY(s, e) \ |
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| .. | .. |
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| 24 | 25 | .padown_offset = BXT_PAD_OWN, \ |
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| 25 | 26 | .padcfglock_offset = BXT_PADCFGLOCK, \ |
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| 26 | 27 | .hostown_offset = BXT_HOSTSW_OWN, \ |
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| 28 | + .is_offset = BXT_GPI_IS, \ |
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| 27 | 29 | .ie_offset = BXT_GPI_IE, \ |
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| 28 | 30 | .gpp_size = 32, \ |
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| 29 | 31 | .pin_base = (s), \ |
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| .. | .. |
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| 117 | 119 | PINCTRL_PIN(82, "TDO"), |
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| 118 | 120 | }; |
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| 119 | 121 | |
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| 120 | | -static const unsigned bxt_north_pwm0_pins[] = { 34 }; |
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| 121 | | -static const unsigned bxt_north_pwm1_pins[] = { 35 }; |
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| 122 | | -static const unsigned bxt_north_pwm2_pins[] = { 36 }; |
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| 123 | | -static const unsigned bxt_north_pwm3_pins[] = { 37 }; |
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| 124 | | -static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 }; |
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| 125 | | -static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 }; |
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| 126 | | -static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 }; |
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| 127 | | -static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 }; |
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| 128 | | -static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 }; |
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| 129 | | -static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 }; |
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| 130 | | -static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 }; |
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| 122 | +static const unsigned int bxt_north_pwm0_pins[] = { 34 }; |
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| 123 | +static const unsigned int bxt_north_pwm1_pins[] = { 35 }; |
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| 124 | +static const unsigned int bxt_north_pwm2_pins[] = { 36 }; |
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| 125 | +static const unsigned int bxt_north_pwm3_pins[] = { 37 }; |
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| 126 | +static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 }; |
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| 127 | +static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 }; |
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| 128 | +static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 }; |
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| 129 | +static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 }; |
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| 130 | +static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 }; |
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| 131 | +static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 }; |
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| 132 | +static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 }; |
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| 131 | 133 | |
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| 132 | 134 | static const struct intel_pingroup bxt_north_groups[] = { |
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| 133 | 135 | PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1), |
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| .. | .. |
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| 260 | 262 | PINCTRL_PIN(71, "GP_SSP_2_TXD"), |
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| 261 | 263 | }; |
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| 262 | 264 | |
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| 263 | | -static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 }; |
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| 264 | | -static const unsigned bxt_northwest_ssp1_pins[] = { |
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| 265 | +static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 }; |
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| 266 | +static const unsigned int bxt_northwest_ssp1_pins[] = { |
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| 265 | 267 | 59, 60, 61, 62, 63, 64, 65 |
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| 266 | 268 | }; |
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| 267 | | -static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 }; |
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| 268 | | -static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 }; |
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| 269 | +static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 }; |
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| 270 | +static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 }; |
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| 269 | 271 | |
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| 270 | 272 | static const struct intel_pingroup bxt_northwest_groups[] = { |
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| 271 | 273 | PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1), |
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| .. | .. |
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| 347 | 349 | PINCTRL_PIN(41, "OSC_CLK_OUT_3"), |
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| 348 | 350 | }; |
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| 349 | 351 | |
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| 350 | | -static const unsigned bxt_west_i2c0_pins[] = { 0, 1 }; |
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| 351 | | -static const unsigned bxt_west_i2c1_pins[] = { 2, 3 }; |
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| 352 | | -static const unsigned bxt_west_i2c2_pins[] = { 4, 5 }; |
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| 353 | | -static const unsigned bxt_west_i2c3_pins[] = { 6, 7 }; |
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| 354 | | -static const unsigned bxt_west_i2c4_pins[] = { 8, 9 }; |
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| 355 | | -static const unsigned bxt_west_i2c5_pins[] = { 10, 11 }; |
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| 356 | | -static const unsigned bxt_west_i2c6_pins[] = { 12, 13 }; |
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| 357 | | -static const unsigned bxt_west_i2c7_pins[] = { 14, 15 }; |
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| 358 | | -static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 }; |
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| 359 | | -static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 }; |
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| 360 | | -static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 }; |
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| 352 | +static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 }; |
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| 353 | +static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 }; |
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| 354 | +static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 }; |
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| 355 | +static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 }; |
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| 356 | +static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 }; |
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| 357 | +static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 }; |
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| 358 | +static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 }; |
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| 359 | +static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 }; |
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| 360 | +static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 }; |
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| 361 | +static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 }; |
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| 362 | +static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 }; |
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| 361 | 363 | |
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| 362 | 364 | static const struct intel_pingroup bxt_west_groups[] = { |
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| 363 | 365 | PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1), |
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| .. | .. |
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| 443 | 445 | PINCTRL_PIN(30, "SDCARD_LVL_WP"), |
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| 444 | 446 | }; |
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| 445 | 447 | |
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| 446 | | -static const unsigned bxt_southwest_emmc0_pins[] = { |
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| 448 | +static const unsigned int bxt_southwest_emmc0_pins[] = { |
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| 447 | 449 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26, |
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| 448 | 450 | }; |
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| 449 | | -static const unsigned bxt_southwest_sdio_pins[] = { |
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| 451 | +static const unsigned int bxt_southwest_sdio_pins[] = { |
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| 450 | 452 | 10, 11, 12, 13, 14, 15, 27, |
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| 451 | 453 | }; |
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| 452 | | -static const unsigned bxt_southwest_sdcard_pins[] = { |
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| 454 | +static const unsigned int bxt_southwest_sdcard_pins[] = { |
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| 453 | 455 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, |
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| 454 | 456 | }; |
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| 455 | 457 | |
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| .. | .. |
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| 526 | 528 | &bxt_west_soc_data, |
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| 527 | 529 | &bxt_southwest_soc_data, |
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| 528 | 530 | &bxt_south_soc_data, |
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| 529 | | - NULL, |
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| 531 | + NULL |
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| 530 | 532 | }; |
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| 531 | 533 | |
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| 532 | 534 | /* APL */ |
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| .. | .. |
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| 611 | 613 | PINCTRL_PIN(77, "SVID0_CLK"), |
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| 612 | 614 | }; |
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| 613 | 615 | |
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| 614 | | -static const unsigned apl_north_pwm0_pins[] = { 34 }; |
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| 615 | | -static const unsigned apl_north_pwm1_pins[] = { 35 }; |
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| 616 | | -static const unsigned apl_north_pwm2_pins[] = { 36 }; |
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| 617 | | -static const unsigned apl_north_pwm3_pins[] = { 37 }; |
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| 618 | | -static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 }; |
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| 619 | | -static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 }; |
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| 620 | | -static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 }; |
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| 616 | +static const unsigned int apl_north_pwm0_pins[] = { 34 }; |
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| 617 | +static const unsigned int apl_north_pwm1_pins[] = { 35 }; |
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| 618 | +static const unsigned int apl_north_pwm2_pins[] = { 36 }; |
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| 619 | +static const unsigned int apl_north_pwm3_pins[] = { 37 }; |
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| 620 | +static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 }; |
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| 621 | +static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 }; |
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| 622 | +static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 }; |
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| 621 | 623 | |
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| 622 | 624 | static const struct intel_pingroup apl_north_groups[] = { |
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| 623 | 625 | PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1), |
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| .. | .. |
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| 743 | 745 | PINCTRL_PIN(76, "GP_SSP_2_TXD"), |
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| 744 | 746 | }; |
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| 745 | 747 | |
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| 746 | | -static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 }; |
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| 747 | | -static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 }; |
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| 748 | | -static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 }; |
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| 749 | | -static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 }; |
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| 748 | +static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 }; |
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| 749 | +static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 }; |
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| 750 | +static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 }; |
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| 751 | +static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 }; |
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| 750 | 752 | |
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| 751 | 753 | static const struct intel_pingroup apl_northwest_groups[] = { |
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| 752 | 754 | PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1), |
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| .. | .. |
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| 833 | 835 | PINCTRL_PIN(46, "SUSPWRDNACK"), |
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| 834 | 836 | }; |
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| 835 | 837 | |
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| 836 | | -static const unsigned apl_west_i2c0_pins[] = { 0, 1 }; |
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| 837 | | -static const unsigned apl_west_i2c1_pins[] = { 2, 3 }; |
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| 838 | | -static const unsigned apl_west_i2c2_pins[] = { 4, 5 }; |
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| 839 | | -static const unsigned apl_west_i2c3_pins[] = { 6, 7 }; |
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| 840 | | -static const unsigned apl_west_i2c4_pins[] = { 8, 9 }; |
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| 841 | | -static const unsigned apl_west_i2c5_pins[] = { 10, 11 }; |
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| 842 | | -static const unsigned apl_west_i2c6_pins[] = { 12, 13 }; |
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| 843 | | -static const unsigned apl_west_i2c7_pins[] = { 14, 15 }; |
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| 844 | | -static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 }; |
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| 838 | +static const unsigned int apl_west_i2c0_pins[] = { 0, 1 }; |
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| 839 | +static const unsigned int apl_west_i2c1_pins[] = { 2, 3 }; |
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| 840 | +static const unsigned int apl_west_i2c2_pins[] = { 4, 5 }; |
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| 841 | +static const unsigned int apl_west_i2c3_pins[] = { 6, 7 }; |
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| 842 | +static const unsigned int apl_west_i2c4_pins[] = { 8, 9 }; |
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| 843 | +static const unsigned int apl_west_i2c5_pins[] = { 10, 11 }; |
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| 844 | +static const unsigned int apl_west_i2c6_pins[] = { 12, 13 }; |
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| 845 | +static const unsigned int apl_west_i2c7_pins[] = { 14, 15 }; |
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| 846 | +static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 }; |
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| 845 | 847 | |
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| 846 | 848 | static const struct intel_pingroup apl_west_groups[] = { |
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| 847 | 849 | PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1), |
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| .. | .. |
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| 939 | 941 | PINCTRL_PIN(42, "LPC_FRAMEB"), |
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| 940 | 942 | }; |
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| 941 | 943 | |
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| 942 | | -static const unsigned apl_southwest_emmc0_pins[] = { |
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| 944 | +static const unsigned int apl_southwest_emmc0_pins[] = { |
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| 943 | 945 | 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29, |
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| 944 | 946 | }; |
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| 945 | | -static const unsigned apl_southwest_sdio_pins[] = { |
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| 947 | +static const unsigned int apl_southwest_sdio_pins[] = { |
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| 946 | 948 | 14, 15, 16, 17, 18, 19, 30, |
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| 947 | 949 | }; |
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| 948 | | -static const unsigned apl_southwest_sdcard_pins[] = { |
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| 950 | +static const unsigned int apl_southwest_sdcard_pins[] = { |
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| 949 | 951 | 20, 21, 22, 23, 24, 25, 26, 27, 28, |
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| 950 | 952 | }; |
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| 951 | | -static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 }; |
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| 953 | +static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 }; |
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| 952 | 954 | |
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| 953 | 955 | static const struct intel_pingroup apl_southwest_groups[] = { |
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| 954 | 956 | PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1), |
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| .. | .. |
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| 990 | 992 | &apl_northwest_soc_data, |
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| 991 | 993 | &apl_west_soc_data, |
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| 992 | 994 | &apl_southwest_soc_data, |
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| 993 | | - NULL, |
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| 995 | + NULL |
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| 994 | 996 | }; |
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| 995 | 997 | |
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| 996 | 998 | static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { |
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| .. | .. |
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| 1003 | 1005 | static const struct platform_device_id bxt_pinctrl_platform_ids[] = { |
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| 1004 | 1006 | { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data }, |
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| 1005 | 1007 | { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data }, |
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| 1006 | | - { }, |
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| 1008 | + { } |
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| 1007 | 1009 | }; |
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| 1008 | 1010 | |
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| 1009 | | -static int bxt_pinctrl_probe(struct platform_device *pdev) |
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| 1010 | | -{ |
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| 1011 | | - const struct intel_pinctrl_soc_data *soc_data = NULL; |
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| 1012 | | - const struct intel_pinctrl_soc_data **soc_table; |
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| 1013 | | - struct acpi_device *adev; |
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| 1014 | | - int i; |
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| 1015 | | - |
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| 1016 | | - adev = ACPI_COMPANION(&pdev->dev); |
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| 1017 | | - if (adev) { |
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| 1018 | | - const struct acpi_device_id *id; |
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| 1019 | | - |
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| 1020 | | - id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev); |
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| 1021 | | - if (!id) |
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| 1022 | | - return -ENODEV; |
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| 1023 | | - |
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| 1024 | | - soc_table = (const struct intel_pinctrl_soc_data **) |
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| 1025 | | - id->driver_data; |
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| 1026 | | - |
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| 1027 | | - for (i = 0; soc_table[i]; i++) { |
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| 1028 | | - if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) { |
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| 1029 | | - soc_data = soc_table[i]; |
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| 1030 | | - break; |
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| 1031 | | - } |
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| 1032 | | - } |
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| 1033 | | - } else { |
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| 1034 | | - const struct platform_device_id *pid; |
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| 1035 | | - |
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| 1036 | | - pid = platform_get_device_id(pdev); |
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| 1037 | | - if (!pid) |
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| 1038 | | - return -ENODEV; |
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| 1039 | | - |
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| 1040 | | - soc_table = (const struct intel_pinctrl_soc_data **) |
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| 1041 | | - pid->driver_data; |
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| 1042 | | - soc_data = soc_table[pdev->id]; |
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| 1043 | | - } |
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| 1044 | | - |
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| 1045 | | - if (!soc_data) |
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| 1046 | | - return -ENODEV; |
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| 1047 | | - |
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| 1048 | | - return intel_pinctrl_probe(pdev, soc_data); |
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| 1049 | | -} |
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| 1050 | | - |
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| 1051 | | -static const struct dev_pm_ops bxt_pinctrl_pm_ops = { |
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| 1052 | | - SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, |
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| 1053 | | - intel_pinctrl_resume) |
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| 1054 | | -}; |
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| 1011 | +static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops); |
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| 1055 | 1012 | |
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| 1056 | 1013 | static struct platform_driver bxt_pinctrl_driver = { |
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| 1057 | | - .probe = bxt_pinctrl_probe, |
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| 1014 | + .probe = intel_pinctrl_probe_by_uid, |
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| 1058 | 1015 | .driver = { |
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| 1059 | 1016 | .name = "broxton-pinctrl", |
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| 1060 | 1017 | .acpi_match_table = bxt_pinctrl_acpi_match, |
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