change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/phy/samsung/phy-exynos5-usbdrd.c
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@@ -1,14 +1,11 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * Samsung EXYNOS5 SoC series USB DRD PHY driver
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+ * Samsung Exynos5 SoC series USB DRD PHY driver
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  *
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  * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
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  *
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  * Copyright (C) 2014 Samsung Electronics Co., Ltd.
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  * Author: Vivek Gautam <gautam.vivek@samsung.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/clk.h>
..
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@@ -19,6 +16,7 @@
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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 #include <linux/of_device.h>
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+#include <linux/iopoll.h>
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 #include <linux/phy/phy.h>
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 #include <linux/platform_device.h>
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 #include <linux/mutex.h>
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@@ -36,7 +34,7 @@
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 #define EXYNOS5_FSEL_24MHZ		0x5
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 #define EXYNOS5_FSEL_50MHZ		0x7
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-/* EXYNOS5: USB 3.0 DRD PHY registers */
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+/* Exynos5: USB 3.0 DRD PHY registers */
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 #define EXYNOS5_DRD_LINKSYSTEM			0x04
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 #define LINKSYSTEM_FLADJ_MASK			(0x3f << 1)
..
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@@ -183,14 +181,14 @@
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  * @utmiclk: clock for utmi+ phy
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  * @itpclk: clock for ITP generation
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  * @drv_data: pointer to SoC level driver data structure
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- * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
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+ * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
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  *	    instances each with its 'phy' and 'phy_cfg'.
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  * @extrefclk: frequency select settings when using 'separate
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  *	       reference clocks' for SS and HS operations
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  * @ref_clk: reference clock to PHY block from which PHY's
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  *	     operational clocks are derived
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- * vbus: VBUS regulator for phy
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- * vbus_boost: Boost regulator for VBUS present on few Exynos boards
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+ * @vbus: VBUS regulator for phy
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+ * @vbus_boost: Boost regulator for VBUS present on few Exynos boards
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  */
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 struct exynos5_usbdrd_phy {
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 	struct device *dev;
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@@ -559,41 +557,25 @@
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 static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
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 			    u32 val, u32 cmd)
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 {
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-	u32 usec = 100;
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 	unsigned int result;
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+	int err;
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 	writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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-	do {
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-		result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
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-		if (result & PHYREG1_CR_ACK)
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-			break;
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-
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-		udelay(1);
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-	} while (usec-- > 0);
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-
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-	if (!usec) {
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-		dev_err(phy_drd->dev,
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-			"CRPORT handshake timeout1 (0x%08x)\n", val);
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-		return -ETIME;
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+	err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
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+				 result, (result & PHYREG1_CR_ACK), 1, 100);
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+	if (err == -ETIMEDOUT) {
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+		dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val);
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+		return err;
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 	}
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-
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-	usec = 100;
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 	writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
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-	do {
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-		result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
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-		if (!(result & PHYREG1_CR_ACK))
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-			break;
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-
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-		udelay(1);
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-	} while (usec-- > 0);
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-
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-	if (!usec) {
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-		dev_err(phy_drd->dev,
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-			"CRPORT handshake timeout2 (0x%08x)\n", val);
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-		return -ETIME;
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+	err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
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+				 result, !(result & PHYREG1_CR_ACK), 1, 100);
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+	if (err == -ETIMEDOUT) {
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+		dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val);
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+		return err;
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 	}
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 	return 0;
..
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@@ -958,11 +940,12 @@
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 	.driver = {
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 		.of_match_table	= exynos5_usbdrd_phy_of_match,
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 		.name		= "exynos5_usb3drd_phy",
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+		.suppress_bind_attrs = true,
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 	}
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 };
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 module_platform_driver(exynos5_usb3drd_phy);
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-MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver");
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+MODULE_DESCRIPTION("Samsung Exynos5 SoCs USB 3.0 DRD controller PHY driver");
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 MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
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 MODULE_LICENSE("GPL v2");
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 MODULE_ALIAS("platform:exynos5_usb3drd_phy");