change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/perf/arm_smmuv3_pmu.c
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@@ -95,6 +95,7 @@
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 #define SMMU_PMCG_PA_SHIFT              12
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 #define SMMU_PMCG_EVCNTR_RDONLY         BIT(0)
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+#define SMMU_PMCG_HARDEN_DISABLE        BIT(1)
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 static int cpuhp_state_num;
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@@ -138,12 +139,42 @@
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 	writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
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 }
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+static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
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+				       struct perf_event *event, int idx);
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+
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+static inline void smmu_pmu_enable_quirk_hip08_09(struct pmu *pmu)
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+{
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+	struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
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+	unsigned int idx;
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+
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+	for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
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+		smmu_pmu_apply_event_filter(smmu_pmu, smmu_pmu->events[idx], idx);
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+
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+	smmu_pmu_enable(pmu);
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+}
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+
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 static inline void smmu_pmu_disable(struct pmu *pmu)
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 {
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 	struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
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 	writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
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 	writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
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+}
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+
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+static inline void smmu_pmu_disable_quirk_hip08_09(struct pmu *pmu)
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+{
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+	struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
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+	unsigned int idx;
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+
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+	/*
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+	 * The global disable of PMU sometimes fail to stop the counting.
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+	 * Harden this by writing an invalid event type to each used counter
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+	 * to forcibly stop counting.
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+	 */
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+	for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
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+		writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
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+
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+	smmu_pmu_disable(pmu);
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 }
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 static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
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@@ -719,7 +750,10 @@
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 	switch (model) {
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 	case IORT_SMMU_V3_PMCG_HISI_HIP08:
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 		/* HiSilicon Erratum 162001800 */
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-		smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
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+		smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY | SMMU_PMCG_HARDEN_DISABLE;
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+		break;
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+	case IORT_SMMU_V3_PMCG_HISI_HIP09:
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+		smmu_pmu->options |= SMMU_PMCG_HARDEN_DISABLE;
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 		break;
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 	}
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@@ -806,6 +840,16 @@
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 	smmu_pmu_get_acpi_options(smmu_pmu);
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+	/*
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+	 * For platforms suffer this quirk, the PMU disable sometimes fails to
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+	 * stop the counters. This will leads to inaccurate or error counting.
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+	 * Forcibly disable the counters with these quirk handler.
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+	 */
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+	if (smmu_pmu->options & SMMU_PMCG_HARDEN_DISABLE) {
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+		smmu_pmu->pmu.pmu_enable = smmu_pmu_enable_quirk_hip08_09;
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+		smmu_pmu->pmu.pmu_disable = smmu_pmu_disable_quirk_hip08_09;
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+	}
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+
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 	/* Pick one CPU to be the preferred one to use */
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 	smmu_pmu->on_cpu = raw_smp_processor_id();
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 	WARN_ON(irq_set_affinity_hint(smmu_pmu->irq,
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@@ -870,6 +914,8 @@
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 static int __init arm_smmu_pmu_init(void)
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 {
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+	int ret;
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+
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 	cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
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 						  "perf/arm/pmcg:online",
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 						  NULL,
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@@ -877,7 +923,11 @@
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 	if (cpuhp_state_num < 0)
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 		return cpuhp_state_num;
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-	return platform_driver_register(&smmu_pmu_driver);
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+	ret = platform_driver_register(&smmu_pmu_driver);
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+	if (ret)
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+		cpuhp_remove_multi_state(cpuhp_state_num);
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+
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+	return ret;
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 }
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 module_init(arm_smmu_pmu_init);
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