| .. | .. |
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| 4 | 4 | #include <linux/hwspinlock.h> |
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| 5 | 5 | #include <linux/module.h> |
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| 6 | 6 | #include <linux/of.h> |
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| 7 | +#include <linux/of_device.h> |
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| 7 | 8 | #include <linux/platform_device.h> |
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| 8 | 9 | #include <linux/regmap.h> |
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| 9 | 10 | #include <linux/nvmem-provider.h> |
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| 10 | 11 | |
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| 11 | 12 | /* PMIC global registers definition */ |
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| 12 | 13 | #define SC27XX_MODULE_EN 0xc08 |
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| 14 | +#define SC2730_MODULE_EN 0x1808 |
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| 13 | 15 | #define SC27XX_EFUSE_EN BIT(6) |
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| 14 | 16 | |
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| 15 | 17 | /* Efuse controller registers definition */ |
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| .. | .. |
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| 49 | 51 | #define SC27XX_EFUSE_POLL_TIMEOUT 3000000 |
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| 50 | 52 | #define SC27XX_EFUSE_POLL_DELAY_US 10000 |
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| 51 | 53 | |
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| 54 | +/* |
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| 55 | + * Since different PMICs of SC27xx series can have different |
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| 56 | + * address , we should save address in the device data structure. |
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| 57 | + */ |
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| 58 | +struct sc27xx_efuse_variant_data { |
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| 59 | + u32 module_en; |
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| 60 | +}; |
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| 61 | + |
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| 52 | 62 | struct sc27xx_efuse { |
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| 53 | 63 | struct device *dev; |
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| 54 | 64 | struct regmap *regmap; |
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| 55 | 65 | struct hwspinlock *hwlock; |
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| 56 | 66 | struct mutex mutex; |
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| 57 | 67 | u32 base; |
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| 68 | + const struct sc27xx_efuse_variant_data *var_data; |
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| 69 | +}; |
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| 70 | + |
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| 71 | +static const struct sc27xx_efuse_variant_data sc2731_edata = { |
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| 72 | + .module_en = SC27XX_MODULE_EN, |
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| 73 | +}; |
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| 74 | + |
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| 75 | +static const struct sc27xx_efuse_variant_data sc2730_edata = { |
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| 76 | + .module_en = SC2730_MODULE_EN, |
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| 58 | 77 | }; |
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| 59 | 78 | |
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| 60 | 79 | /* |
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| .. | .. |
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| 106 | 125 | static int sc27xx_efuse_read(void *context, u32 offset, void *val, size_t bytes) |
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| 107 | 126 | { |
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| 108 | 127 | struct sc27xx_efuse *efuse = context; |
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| 109 | | - u32 buf; |
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| 128 | + u32 buf, blk_index = offset / SC27XX_EFUSE_BLOCK_WIDTH; |
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| 129 | + u32 blk_offset = (offset % SC27XX_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE; |
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| 110 | 130 | int ret; |
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| 111 | 131 | |
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| 112 | | - if (offset > SC27XX_EFUSE_BLOCK_MAX || bytes > SC27XX_EFUSE_BLOCK_WIDTH) |
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| 132 | + if (blk_index > SC27XX_EFUSE_BLOCK_MAX || |
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| 133 | + bytes > SC27XX_EFUSE_BLOCK_WIDTH) |
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| 113 | 134 | return -EINVAL; |
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| 114 | 135 | |
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| 115 | 136 | ret = sc27xx_efuse_lock(efuse); |
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| .. | .. |
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| 117 | 138 | return ret; |
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| 118 | 139 | |
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| 119 | 140 | /* Enable the efuse controller. */ |
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| 120 | | - ret = regmap_update_bits(efuse->regmap, SC27XX_MODULE_EN, |
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| 141 | + ret = regmap_update_bits(efuse->regmap, efuse->var_data->module_en, |
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| 121 | 142 | SC27XX_EFUSE_EN, SC27XX_EFUSE_EN); |
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| 122 | 143 | if (ret) |
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| 123 | 144 | goto unlock_efuse; |
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| .. | .. |
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| 133 | 154 | /* Set the block address to be read. */ |
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| 134 | 155 | ret = regmap_write(efuse->regmap, |
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| 135 | 156 | efuse->base + SC27XX_EFUSE_BLOCK_INDEX, |
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| 136 | | - offset & SC27XX_EFUSE_BLOCK_MASK); |
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| 157 | + blk_index & SC27XX_EFUSE_BLOCK_MASK); |
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| 137 | 158 | if (ret) |
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| 138 | 159 | goto disable_efuse; |
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| 139 | 160 | |
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| .. | .. |
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| 167 | 188 | |
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| 168 | 189 | disable_efuse: |
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| 169 | 190 | /* Disable the efuse controller after reading. */ |
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| 170 | | - regmap_update_bits(efuse->regmap, SC27XX_MODULE_EN, SC27XX_EFUSE_EN, 0); |
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| 191 | + regmap_update_bits(efuse->regmap, efuse->var_data->module_en, SC27XX_EFUSE_EN, 0); |
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| 171 | 192 | unlock_efuse: |
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| 172 | 193 | sc27xx_efuse_unlock(efuse); |
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| 173 | 194 | |
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| 174 | | - if (!ret) |
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| 195 | + if (!ret) { |
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| 196 | + buf >>= blk_offset; |
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| 175 | 197 | memcpy(val, &buf, bytes); |
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| 198 | + } |
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| 176 | 199 | |
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| 177 | 200 | return ret; |
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| 178 | 201 | } |
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| .. | .. |
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| 207 | 230 | return ret; |
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| 208 | 231 | } |
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| 209 | 232 | |
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| 210 | | - efuse->hwlock = hwspin_lock_request_specific(ret); |
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| 233 | + efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret); |
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| 211 | 234 | if (!efuse->hwlock) { |
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| 212 | 235 | dev_err(&pdev->dev, "failed to request hwspinlock\n"); |
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| 213 | 236 | return -ENXIO; |
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| .. | .. |
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| 215 | 238 | |
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| 216 | 239 | mutex_init(&efuse->mutex); |
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| 217 | 240 | efuse->dev = &pdev->dev; |
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| 218 | | - platform_set_drvdata(pdev, efuse); |
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| 241 | + efuse->var_data = of_device_get_match_data(&pdev->dev); |
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| 219 | 242 | |
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| 220 | 243 | econfig.stride = 1; |
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| 221 | 244 | econfig.word_size = 1; |
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| .. | .. |
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| 228 | 251 | nvmem = devm_nvmem_register(&pdev->dev, &econfig); |
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| 229 | 252 | if (IS_ERR(nvmem)) { |
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| 230 | 253 | dev_err(&pdev->dev, "failed to register nvmem config\n"); |
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| 231 | | - hwspin_lock_free(efuse->hwlock); |
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| 232 | 254 | return PTR_ERR(nvmem); |
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| 233 | 255 | } |
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| 234 | 256 | |
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| 235 | 257 | return 0; |
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| 236 | 258 | } |
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| 237 | 259 | |
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| 238 | | -static int sc27xx_efuse_remove(struct platform_device *pdev) |
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| 239 | | -{ |
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| 240 | | - struct sc27xx_efuse *efuse = platform_get_drvdata(pdev); |
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| 241 | | - |
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| 242 | | - hwspin_lock_free(efuse->hwlock); |
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| 243 | | - return 0; |
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| 244 | | -} |
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| 245 | | - |
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| 246 | 260 | static const struct of_device_id sc27xx_efuse_of_match[] = { |
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| 247 | | - { .compatible = "sprd,sc2731-efuse" }, |
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| 261 | + { .compatible = "sprd,sc2731-efuse", .data = &sc2731_edata}, |
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| 262 | + { .compatible = "sprd,sc2730-efuse", .data = &sc2730_edata}, |
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| 248 | 263 | { } |
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| 249 | 264 | }; |
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| 250 | 265 | |
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| 251 | 266 | static struct platform_driver sc27xx_efuse_driver = { |
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| 252 | 267 | .probe = sc27xx_efuse_probe, |
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| 253 | | - .remove = sc27xx_efuse_remove, |
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| 254 | 268 | .driver = { |
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| 255 | 269 | .name = "sc27xx-efuse", |
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| 256 | 270 | .of_match_table = sc27xx_efuse_of_match, |
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