change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/net/wan/ixp4xx_hss.c
..
..
@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Intel IXP4xx HSS (synchronous serial port) driver for Linux
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  *
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  * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of version 2 of the GNU General Public License
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- * as published by the Free Software Foundation.
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  */
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 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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..
@@ -20,10 +17,11 @@
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 #include <linux/io.h>
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 #include <linux/kernel.h>
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 #include <linux/platform_device.h>
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+#include <linux/platform_data/wan_ixp4xx_hss.h>
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 #include <linux/poll.h>
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 #include <linux/slab.h>
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-#include <mach/npe.h>
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-#include <mach/qmgr.h>
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+#include <linux/soc/ixp4xx/npe.h>
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+#include <linux/soc/ixp4xx/qmgr.h>
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 #define DEBUG_DESC		0
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 #define DEBUG_RX		0
..
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@@ -246,7 +244,7 @@
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 #ifdef __ARMEB__
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 typedef struct sk_buff buffer_t;
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 #define free_buffer dev_kfree_skb
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-#define free_buffer_irq dev_kfree_skb_irq
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+#define free_buffer_irq dev_consume_skb_irq
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 #else
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 typedef void buffer_t;
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 #define free_buffer kfree
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@@ -1185,14 +1183,14 @@
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 	}
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 }
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-static u32 check_clock(u32 rate, u32 a, u32 b, u32 c,
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+static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
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 		       u32 *best, u32 *best_diff, u32 *reg)
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 {
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 	/* a is 10-bit, b is 10-bit, c is 12-bit */
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 	u64 new_rate;
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 	u32 new_diff;
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-	new_rate = ixp4xx_timer_freq * (u64)(c + 1);
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+	new_rate = timer_freq * (u64)(c + 1);
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 	do_div(new_rate, a * (c + 1) + b + 1);
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 	new_diff = abs((u32)new_rate - rate);
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@@ -1204,40 +1202,43 @@
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 	return new_diff;
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 }
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-static void find_best_clock(u32 rate, u32 *best, u32 *reg)
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+static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
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 {
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 	u32 a, b, diff = 0xFFFFFFFF;
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-	a = ixp4xx_timer_freq / rate;
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+	a = timer_freq / rate;
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 	if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
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-		check_clock(rate, 0x3FF, 1, 1, best, &diff, reg);
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+		check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
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 		return;
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 	}
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 	if (a == 0) { /* > 66.666 MHz */
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 		a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
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-		rate = ixp4xx_timer_freq;
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+		rate = timer_freq;
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 	}
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-	if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */
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-		check_clock(rate, a - 1, 1, 1, best, &diff, reg);
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+	if (rate * a == timer_freq) { /* don't divide by 0 later */
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+		check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
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 		return;
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 	}
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 	for (b = 0; b < 0x400; b++) {
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 		u64 c = (b + 1) * (u64)rate;
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-		do_div(c, ixp4xx_timer_freq - rate * a);
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+		do_div(c, timer_freq - rate * a);
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 		c--;
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 		if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
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 			if (b == 0 && /* also try a bit higher rate */
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-			    !check_clock(rate, a - 1, 1, 1, best, &diff, reg))
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+			    !check_clock(timer_freq, rate, a - 1, 1, 1, best,
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+					 &diff, reg))
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 				return;
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-			check_clock(rate, a, b, 0xFFF, best, &diff, reg);
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+			check_clock(timer_freq, rate, a, b, 0xFFF, best,
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+				    &diff, reg);
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 			return;
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 		}
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-		if (!check_clock(rate, a, b, c, best, &diff, reg))
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+		if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
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 			return;
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-		if (!check_clock(rate, a, b, c + 1, best, &diff, reg))
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+		if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
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+				 reg))
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 			return;
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 	}
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 }
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@@ -1288,8 +1289,9 @@
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 		port->clock_type = clk; /* Update settings */
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 		if (clk == CLOCK_INT)
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-			find_best_clock(new_line.clock_rate, &port->clock_rate,
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-					&port->clock_reg);
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+			find_best_clock(port->plat->timer_freq,
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+					new_line.clock_rate,
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+					&port->clock_rate, &port->clock_reg);
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 		else {
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 			port->clock_rate = 0;
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 			port->clock_reg = CLK42X_SPEED_2048KHZ;