| .. | .. |
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| 404 | 404 | case PHY_INTERFACE_MODE_TRGMII: |
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| 405 | 405 | trgint = 1; |
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| 406 | 406 | if (priv->id == ID_MT7621) { |
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| 407 | | - /* PLL frequency: 150MHz: 1.2GBit */ |
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| 407 | + /* PLL frequency: 125MHz: 1.0GBit */ |
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| 408 | 408 | if (xtal == HWTRAP_XTAL_40MHZ) |
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| 409 | | - ncpo1 = 0x0780; |
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| 409 | + ncpo1 = 0x0640; |
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| 410 | 410 | if (xtal == HWTRAP_XTAL_25MHZ) |
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| 411 | 411 | ncpo1 = 0x0a00; |
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| 412 | 412 | } else { /* PLL frequency: 250MHz: 2.0Gbit */ |
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| .. | .. |
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| 966 | 966 | mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port))); |
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| 967 | 967 | |
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| 968 | 968 | /* Set CPU port number */ |
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| 969 | | - if (priv->id == ID_MT7621) |
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| 969 | + if (priv->id == ID_MT7530 || priv->id == ID_MT7621) |
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| 970 | 970 | mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); |
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| 971 | 971 | |
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| 972 | 972 | /* CPU port gets connected to all user ports of |
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