~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,18 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
4		- *
5		- * This program is free software; you can redistribute it and/or modify
6		- * it under the terms of the GNU General Public License version 2 as
7		- * published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13		- *
14		- * You should have received a copy of the GNU General Public License
15		- * along with this program. If not, see <http://www.gnu.org/licenses/>.
16	5	*/
17	6
18	7	#define pr_fmt(fmt) "GICv3: " fmt
..	..	@@ -27,8 +16,11 @@
27	16	#include <linux/of_address.h>
28	17	#include <linux/of_irq.h>
29	18	#include <linux/percpu.h>
	19	+#include <linux/refcount.h>
30	20	#include <linux/slab.h>
	21	+#include <linux/syscore_ops.h>
31	22	#include <linux/wakeup_reason.h>
	23	+#include <trace/hooks/gic_v3.h>
32	24
33	25
34	26	#include <linux/irqchip.h>
..	..	@@ -41,7 +33,17 @@
41	33	#include <asm/smp_plat.h>
42	34	#include <asm/virt.h>
43	35
	36	+#include <trace/hooks/gic.h>
	37	+
44	38	#include "irq-gic-common.h"
	39	+
	40	+#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
	41	+
	42	+#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
	43	+#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
	44	+#define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2)
	45	+
	46	+#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
45	47
46	48	struct redist_region {
47	49	void __iomem *redist_base;
..	..	@@ -49,21 +51,73 @@
49	51	bool single_redist;
50	52	};
51	53
52		-struct gic_chip_data {
53		- struct fwnode_handle *fwnode;
54		- void __iomem *dist_base;
55		- struct redist_region *redist_regions;
56		- struct rdists rdists;
57		- struct irq_domain *domain;
58		- u64 redist_stride;
59		- u32 nr_redist_regions;
60		- bool has_rss;
61		- unsigned int irq_nr;
62		- struct partition_desc *ppi_descs[16];
63		-};
	54	+static DEFINE_STATIC_KEY_FALSE(gic_arm64_2941627_erratum);
64	55
65	56	static struct gic_chip_data gic_data __read_mostly;
66	57	static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
	58	+
	59	+#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
	60	+#define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
	61	+#define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
	62	+
	63	+/*
	64	+ * The behaviours of RPR and PMR registers differ depending on the value of
	65	+ * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
	66	+ * distributor and redistributors depends on whether security is enabled in the
	67	+ * GIC.
	68	+ *
	69	+ * When security is enabled, non-secure priority values from the (re)distributor
	70	+ * are presented to the GIC CPUIF as follow:
	71	+ * (GIC_(R)DIST_PRI[irq] >> 1) \| 0x80;
	72	+ *
	73	+ * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
	74	+ * EL1 are subject to a similar operation thus matching the priorities presented
	75	+ * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
	76	+ * these values are unchanched by the GIC.
	77	+ *
	78	+ * see GICv3/GICv4 Architecture Specification (IHI0069D):
	79	+ * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
	80	+ * priorities.
	81	+ * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
	82	+ * interrupt.
	83	+ */
	84	+static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
	85	+
	86	+/*
	87	+ * Global static key controlling whether an update to PMR allowing more
	88	+ * interrupts requires to be propagated to the redistributor (DSB SY).
	89	+ * And this needs to be exported for modules to be able to enable
	90	+ * interrupts...
	91	+ */
	92	+DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
	93	+EXPORT_SYMBOL(gic_pmr_sync);
	94	+
	95	+DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
	96	+EXPORT_SYMBOL(gic_nonsecure_priorities);
	97	+
	98	+/*
	99	+ * When the Non-secure world has access to group 0 interrupts (as a
	100	+ * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
	101	+ * return the Distributor's view of the interrupt priority.
	102	+ *
	103	+ * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
	104	+ * written by software is moved to the Non-secure range by the Distributor.
	105	+ *
	106	+ * If both are true (which is when gic_nonsecure_priorities gets enabled),
	107	+ * we need to shift down the priority programmed by software to match it
	108	+ * against the value returned by ICC_RPR_EL1.
	109	+ */
	110	+#define GICD_INT_RPR_PRI(priority) \
	111	+ ({ \
	112	+ u32 __priority = (priority); \
	113	+ if (static_branch_unlikely(&gic_nonsecure_priorities)) \
	114	+ __priority = 0x80 \| (__priority >> 1); \
	115	+ \
	116	+ __priority; \
	117	+ })
	118	+
	119	+/* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
	120	+static refcount_t *ppi_nmi_refs;
67	121
68	122	static struct gic_kvm_info gic_v3_kvm_info;
69	123	static DEFINE_PER_CPU(bool, has_rss);
..	..	@@ -76,32 +130,82 @@
76	130	/* Our default, arbitrary priority value. Linux only uses one anyway. */
77	131	#define DEFAULT_PMR_VALUE 0xf0
78	132
	133	+enum gic_intid_range {
	134	+ SGI_RANGE,
	135	+ PPI_RANGE,
	136	+ SPI_RANGE,
	137	+ EPPI_RANGE,
	138	+ ESPI_RANGE,
	139	+ LPI_RANGE,
	140	+ __INVALID_RANGE__
	141	+};
	142	+
	143	+static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
	144	+{
	145	+ switch (hwirq) {
	146	+ case 0 ... 15:
	147	+ return SGI_RANGE;
	148	+ case 16 ... 31:
	149	+ return PPI_RANGE;
	150	+ case 32 ... 1019:
	151	+ return SPI_RANGE;
	152	+ case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
	153	+ return EPPI_RANGE;
	154	+ case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
	155	+ return ESPI_RANGE;
	156	+ case 8192 ... GENMASK(23, 0):
	157	+ return LPI_RANGE;
	158	+ default:
	159	+ return __INVALID_RANGE__;
	160	+ }
	161	+}
	162	+
	163	+static enum gic_intid_range get_intid_range(struct irq_data *d)
	164	+{
	165	+ return __get_intid_range(d->hwirq);
	166	+}
	167	+
79	168	static inline unsigned int gic_irq(struct irq_data *d)
80	169	{
81	170	return d->hwirq;
82	171	}
83	172
84		-static inline int gic_irq_in_rdist(struct irq_data *d)
	173	+static inline bool gic_irq_in_rdist(struct irq_data *d)
85	174	{
86		- return gic_irq(d) < 32;
	175	+ switch (get_intid_range(d)) {
	176	+ case SGI_RANGE:
	177	+ case PPI_RANGE:
	178	+ case EPPI_RANGE:
	179	+ return true;
	180	+ default:
	181	+ return false;
	182	+ }
87	183	}
88	184
89	185	static inline void __iomem gic_dist_base(struct irq_data d)
90	186	{
91		- if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
	187	+ switch (get_intid_range(d)) {
	188	+ case SGI_RANGE:
	189	+ case PPI_RANGE:
	190	+ case EPPI_RANGE:
	191	+ /* SGI+PPI -> SGI_base for this CPU */
92	192	return gic_data_rdist_sgi_base();
93	193
94		- if (d->hwirq <= 1023) /* SPI -> dist_base */
	194	+ case SPI_RANGE:
	195	+ case ESPI_RANGE:
	196	+ /* SPI -> dist_base */
95	197	return gic_data.dist_base;
96	198
97		- return NULL;
	199	+ default:
	200	+ return NULL;
	201	+ }
98	202	}
99	203
100		-static void gic_do_wait_for_rwp(void __iomem *base)
	204	+static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
101	205	{
102	206	u32 count = 1000000; /* 1s! */
103	207
104		- while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
	208	+ while (readl_relaxed(base + GICD_CTLR) & bit) {
105	209	count--;
106	210	if (!count) {
107	211	pr_err_ratelimited("RWP timeout, gone fishing\n");
..	..	@@ -109,19 +213,19 @@
109	213	}
110	214	cpu_relax();
111	215	udelay(1);
112		- };
	216	+ }
113	217	}
114	218
115	219	/* Wait for completion of a distributor change */
116	220	static void gic_dist_wait_for_rwp(void)
117	221	{
118		- gic_do_wait_for_rwp(gic_data.dist_base);
	222	+ gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
119	223	}
120	224
121	225	/* Wait for completion of a redistributor change */
122	226	static void gic_redist_wait_for_rwp(void)
123	227	{
124		- gic_do_wait_for_rwp(gic_data_rdist_rd_base());
	228	+ gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
125	229	}
126	230
127	231	#ifdef CONFIG_ARM64
..	..	@@ -140,6 +244,9 @@
140	244	void __iomem *rbase;
141	245	u32 count = 1000000; /* 1s! */
142	246	u32 val;
	247	+
	248	+ if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
	249	+ return;
143	250
144	251	rbase = gic_data_rdist_rd_base();
145	252
..	..	@@ -163,7 +270,7 @@
163	270	break;
164	271	cpu_relax();
165	272	udelay(1);
166		- };
	273	+ }
167	274	if (!count)
168	275	pr_err_ratelimited("redistributor failed to %s...\n",
169	276	enable ? "wakeup" : "sleep");
..	..	@@ -172,24 +279,80 @@
172	279	/*
173	280	* Routines to disable, enable, EOI and route interrupts
174	281	*/
	282	+static u32 convert_offset_index(struct irq_data d, u32 offset, u32 index)
	283	+{
	284	+ switch (get_intid_range(d)) {
	285	+ case SGI_RANGE:
	286	+ case PPI_RANGE:
	287	+ case SPI_RANGE:
	288	+ *index = d->hwirq;
	289	+ return offset;
	290	+ case EPPI_RANGE:
	291	+ /*
	292	+ * Contrary to the ESPI range, the EPPI range is contiguous
	293	+ * to the PPI range in the registers, so let's adjust the
	294	+ * displacement accordingly. Consistency is overrated.
	295	+ */
	296	+ *index = d->hwirq - EPPI_BASE_INTID + 32;
	297	+ return offset;
	298	+ case ESPI_RANGE:
	299	+ *index = d->hwirq - ESPI_BASE_INTID;
	300	+ switch (offset) {
	301	+ case GICD_ISENABLER:
	302	+ return GICD_ISENABLERnE;
	303	+ case GICD_ICENABLER:
	304	+ return GICD_ICENABLERnE;
	305	+ case GICD_ISPENDR:
	306	+ return GICD_ISPENDRnE;
	307	+ case GICD_ICPENDR:
	308	+ return GICD_ICPENDRnE;
	309	+ case GICD_ISACTIVER:
	310	+ return GICD_ISACTIVERnE;
	311	+ case GICD_ICACTIVER:
	312	+ return GICD_ICACTIVERnE;
	313	+ case GICD_IPRIORITYR:
	314	+ return GICD_IPRIORITYRnE;
	315	+ case GICD_ICFGR:
	316	+ return GICD_ICFGRnE;
	317	+ case GICD_IROUTER:
	318	+ return GICD_IROUTERnE;
	319	+ default:
	320	+ break;
	321	+ }
	322	+ break;
	323	+ default:
	324	+ break;
	325	+ }
	326	+
	327	+ WARN_ON(1);
	328	+ *index = d->hwirq;
	329	+ return offset;
	330	+}
	331	+
175	332	static int gic_peek_irq(struct irq_data *d, u32 offset)
176	333	{
177		- u32 mask = 1 << (gic_irq(d) % 32);
178	334	void __iomem *base;
	335	+ u32 index, mask;
	336	+
	337	+ offset = convert_offset_index(d, offset, &index);
	338	+ mask = 1 << (index % 32);
179	339
180	340	if (gic_irq_in_rdist(d))
181	341	base = gic_data_rdist_sgi_base();
182	342	else
183	343	base = gic_data.dist_base;
184	344
185		- return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
	345	+ return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
186	346	}
187	347
188	348	static void gic_poke_irq(struct irq_data *d, u32 offset)
189	349	{
190		- u32 mask = 1 << (gic_irq(d) % 32);
191	350	void (*rwp_wait)(void);
192	351	void __iomem *base;
	352	+ u32 index, mask;
	353	+
	354	+ offset = convert_offset_index(d, offset, &index);
	355	+ mask = 1 << (index % 32);
193	356
194	357	if (gic_irq_in_rdist(d)) {
195	358	base = gic_data_rdist_sgi_base();
..	..	@@ -199,7 +362,7 @@
199	362	rwp_wait = gic_dist_wait_for_rwp;
200	363	}
201	364
202		- writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
	365	+ writel_relaxed(mask, base + offset + (index / 32) * 4);
203	366	rwp_wait();
204	367	}
205	368
..	..	@@ -228,21 +391,18 @@
228	391	gic_poke_irq(d, GICD_ISENABLER);
229	392	}
230	393
231		-#ifdef CONFIG_ARCH_ROCKCHIP
232		-static int gic_retrigger(struct irq_data *d)
	394	+static inline bool gic_supports_nmi(void)
233	395	{
234		- gic_poke_irq(d, GICD_ISPENDR);
235		- /* the genirq layer expects 0 if we can't retrigger in hardware */
236		- return 0;
	396	+ return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
	397	+ static_branch_likely(&supports_pseudo_nmis);
237	398	}
238		-#endif
239	399
240	400	static int gic_irq_set_irqchip_state(struct irq_data *d,
241	401	enum irqchip_irq_state which, bool val)
242	402	{
243	403	u32 reg;
244	404
245		- if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
	405	+ if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
246	406	return -EINVAL;
247	407
248	408	switch (which) {
..	..	@@ -269,7 +429,7 @@
269	429	static int gic_irq_get_irqchip_state(struct irq_data *d,
270	430	enum irqchip_irq_state which, bool *val)
271	431	{
272		- if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
	432	+ if (d->hwirq >= 8192) /* PPI/SPI only */
273	433	return -EINVAL;
274	434
275	435	switch (which) {
..	..	@@ -292,9 +452,131 @@
292	452	return 0;
293	453	}
294	454
	455	+static void gic_irq_set_prio(struct irq_data *d, u8 prio)
	456	+{
	457	+ void __iomem *base = gic_dist_base(d);
	458	+ u32 offset, index;
	459	+
	460	+ offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
	461	+
	462	+ writeb_relaxed(prio, base + offset + index);
	463	+}
	464	+
	465	+static u32 gic_get_ppi_index(struct irq_data *d)
	466	+{
	467	+ switch (get_intid_range(d)) {
	468	+ case PPI_RANGE:
	469	+ return d->hwirq - 16;
	470	+ case EPPI_RANGE:
	471	+ return d->hwirq - EPPI_BASE_INTID + 16;
	472	+ default:
	473	+ unreachable();
	474	+ }
	475	+}
	476	+
	477	+static int gic_irq_nmi_setup(struct irq_data *d)
	478	+{
	479	+ struct irq_desc *desc = irq_to_desc(d->irq);
	480	+
	481	+ if (!gic_supports_nmi())
	482	+ return -EINVAL;
	483	+
	484	+ if (gic_peek_irq(d, GICD_ISENABLER)) {
	485	+ pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
	486	+ return -EINVAL;
	487	+ }
	488	+
	489	+ /*
	490	+ * A secondary irq_chip should be in charge of LPI request,
	491	+ * it should not be possible to get there
	492	+ */
	493	+ if (WARN_ON(gic_irq(d) >= 8192))
	494	+ return -EINVAL;
	495	+
	496	+ /* desc lock should already be held */
	497	+ if (gic_irq_in_rdist(d)) {
	498	+ u32 idx = gic_get_ppi_index(d);
	499	+
	500	+ /* Setting up PPI as NMI, only switch handler for first NMI */
	501	+ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
	502	+ refcount_set(&ppi_nmi_refs[idx], 1);
	503	+ desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
	504	+ }
	505	+ } else {
	506	+ desc->handle_irq = handle_fasteoi_nmi;
	507	+ }
	508	+
	509	+ gic_irq_set_prio(d, GICD_INT_NMI_PRI);
	510	+
	511	+ return 0;
	512	+}
	513	+
	514	+static void gic_irq_nmi_teardown(struct irq_data *d)
	515	+{
	516	+ struct irq_desc *desc = irq_to_desc(d->irq);
	517	+
	518	+ if (WARN_ON(!gic_supports_nmi()))
	519	+ return;
	520	+
	521	+ if (gic_peek_irq(d, GICD_ISENABLER)) {
	522	+ pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
	523	+ return;
	524	+ }
	525	+
	526	+ /*
	527	+ * A secondary irq_chip should be in charge of LPI request,
	528	+ * it should not be possible to get there
	529	+ */
	530	+ if (WARN_ON(gic_irq(d) >= 8192))
	531	+ return;
	532	+
	533	+ /* desc lock should already be held */
	534	+ if (gic_irq_in_rdist(d)) {
	535	+ u32 idx = gic_get_ppi_index(d);
	536	+
	537	+ /* Tearing down NMI, only switch handler for last NMI */
	538	+ if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
	539	+ desc->handle_irq = handle_percpu_devid_irq;
	540	+ } else {
	541	+ desc->handle_irq = handle_fasteoi_irq;
	542	+ }
	543	+
	544	+ gic_irq_set_prio(d, GICD_INT_DEF_PRI);
	545	+}
	546	+
	547	+static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
	548	+{
	549	+ enum gic_intid_range range;
	550	+
	551	+ if (!static_branch_unlikely(&gic_arm64_2941627_erratum))
	552	+ return false;
	553	+
	554	+ range = get_intid_range(d);
	555	+
	556	+ /*
	557	+ * The workaround is needed if the IRQ is an SPI and
	558	+ * the target cpu is different from the one we are
	559	+ * executing on.
	560	+ */
	561	+ return (range == SPI_RANGE \|\| range == ESPI_RANGE) &&
	562	+ !cpumask_test_cpu(raw_smp_processor_id(),
	563	+ irq_data_get_effective_affinity_mask(d));
	564	+}
	565	+
295	566	static void gic_eoi_irq(struct irq_data *d)
296	567	{
297		- gic_write_eoir(gic_irq(d));
	568	+ write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
	569	+ isb();
	570	+
	571	+ if (gic_arm64_erratum_2941627_needed(d)) {
	572	+ /*
	573	+ * Make sure the GIC stream deactivate packet
	574	+ * issued by ICC_EOIR1_EL1 has completed before
	575	+ * deactivating through GICD_IACTIVER.
	576	+ */
	577	+ dsb(sy);
	578	+ gic_poke_irq(d, GICD_ICACTIVER);
	579	+ }
298	580	}
299	581
300	582	static void gic_eoimode1_eoi_irq(struct irq_data *d)
..	..	@@ -305,22 +587,31 @@
305	587	*/
306	588	if (gic_irq(d) >= 8192 \|\| irqd_is_forwarded_to_vcpu(d))
307	589	return;
308		- gic_write_dir(gic_irq(d));
	590	+
	591	+ if (!gic_arm64_erratum_2941627_needed(d))
	592	+ gic_write_dir(gic_irq(d));
	593	+ else
	594	+ gic_poke_irq(d, GICD_ICACTIVER);
309	595	}
310	596
311	597	static int gic_set_type(struct irq_data *d, unsigned int type)
312	598	{
	599	+ enum gic_intid_range range;
313	600	unsigned int irq = gic_irq(d);
314	601	void (*rwp_wait)(void);
315	602	void __iomem *base;
	603	+ u32 offset, index;
	604	+ int ret;
	605	+
	606	+ range = get_intid_range(d);
316	607
317	608	/* Interrupt configuration for SGIs can't be changed */
318		- if (irq < 16)
319		- return -EINVAL;
	609	+ if (range == SGI_RANGE)
	610	+ return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
320	611
321	612	/* SPIs have restrictions on the supported types */
322		- if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
323		- type != IRQ_TYPE_EDGE_RISING)
	613	+ if ((range == SPI_RANGE \|\| range == ESPI_RANGE) &&
	614	+ type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
324	615	return -EINVAL;
325	616
326	617	if (gic_irq_in_rdist(d)) {
..	..	@@ -331,11 +622,23 @@
331	622	rwp_wait = gic_dist_wait_for_rwp;
332	623	}
333	624
334		- return gic_configure_irq(irq, type, base, rwp_wait);
	625	+ offset = convert_offset_index(d, GICD_ICFGR, &index);
	626	+
	627	+ ret = gic_configure_irq(index, type, base + offset, rwp_wait);
	628	+ if (ret && (range == PPI_RANGE \|\| range == EPPI_RANGE)) {
	629	+ /* Misconfigured PPIs are usually not fatal */
	630	+ pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
	631	+ ret = 0;
	632	+ }
	633	+
	634	+ return ret;
335	635	}
336	636
337	637	static int gic_irq_set_vcpu_affinity(struct irq_data d, void vcpu)
338	638	{
	639	+ if (get_intid_range(d) == SGI_RANGE)
	640	+ return -EINVAL;
	641	+
339	642	if (vcpu)
340	643	irqd_set_forwarded_to_vcpu(d);
341	644	else
..	..	@@ -355,54 +658,143 @@
355	658	return aff;
356	659	}
357	660
	661	+static void gic_deactivate_unhandled(u32 irqnr)
	662	+{
	663	+ if (static_branch_likely(&supports_deactivate_key)) {
	664	+ if (irqnr < 8192)
	665	+ gic_write_dir(irqnr);
	666	+ } else {
	667	+ gic_write_eoir(irqnr);
	668	+ }
	669	+}
	670	+
	671	+static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
	672	+{
	673	+ bool irqs_enabled = interrupts_enabled(regs);
	674	+ int err;
	675	+
	676	+ if (irqs_enabled)
	677	+ nmi_enter();
	678	+
	679	+ if (static_branch_likely(&supports_deactivate_key))
	680	+ gic_write_eoir(irqnr);
	681	+ /*
	682	+ * Leave the PSR.I bit set to prevent other NMIs to be
	683	+ * received while handling this one.
	684	+ * PSR.I will be restored when we ERET to the
	685	+ * interrupted context.
	686	+ */
	687	+ err = handle_domain_nmi(gic_data.domain, irqnr, regs);
	688	+ if (err)
	689	+ gic_deactivate_unhandled(irqnr);
	690	+
	691	+ if (irqs_enabled)
	692	+ nmi_exit();
	693	+}
	694	+
	695	+static u32 do_read_iar(struct pt_regs *regs)
	696	+{
	697	+ u32 iar;
	698	+
	699	+ if (gic_supports_nmi() && unlikely(!interrupts_enabled(regs))) {
	700	+ u64 pmr;
	701	+
	702	+ /*
	703	+ * We were in a context with IRQs disabled. However, the
	704	+ * entry code has set PMR to a value that allows any
	705	+ * interrupt to be acknowledged, and not just NMIs. This can
	706	+ * lead to surprising effects if the NMI has been retired in
	707	+ * the meantime, and that there is an IRQ pending. The IRQ
	708	+ * would then be taken in NMI context, something that nobody
	709	+ * wants to debug twice.
	710	+ *
	711	+ * Until we sort this, drop PMR again to a level that will
	712	+ * actually only allow NMIs before reading IAR, and then
	713	+ * restore it to what it was.
	714	+ */
	715	+ pmr = gic_read_pmr();
	716	+ gic_pmr_mask_irqs();
	717	+ isb();
	718	+
	719	+ iar = gic_read_iar();
	720	+
	721	+ gic_write_pmr(pmr);
	722	+ } else {
	723	+ iar = gic_read_iar();
	724	+ }
	725	+
	726	+ return iar;
	727	+}
	728	+
358	729	static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
359	730	{
360	731	u32 irqnr;
361	732
362		- do {
363		- irqnr = gic_read_iar();
	733	+ irqnr = do_read_iar(regs);
364	734
365		- if (likely(irqnr > 15 && irqnr < 1020) \|\| irqnr >= 8192) {
366		- int err;
	735	+ /* Check for special IDs first */
	736	+ if ((irqnr >= 1020 && irqnr <= 1023))
	737	+ return;
367	738
368		- if (static_branch_likely(&supports_deactivate_key))
369		- gic_write_eoir(irqnr);
370		- else
371		- isb();
	739	+ if (gic_supports_nmi() &&
	740	+ unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) {
	741	+ gic_handle_nmi(irqnr, regs);
	742	+ return;
	743	+ }
372	744
373		- err = handle_domain_irq(gic_data.domain, irqnr, regs);
374		- if (err) {
375		- WARN_ONCE(true, "Unexpected interrupt received!\n");
376		- log_abnormal_wakeup_reason(
377		- "unexpected HW IRQ %u", irqnr);
378		- if (static_branch_likely(&supports_deactivate_key)) {
379		- if (irqnr < 8192)
380		- gic_write_dir(irqnr);
381		- } else {
382		- gic_write_eoir(irqnr);
383		- }
384		- }
385		- continue;
386		- }
387		- if (irqnr < 16) {
388		- gic_write_eoir(irqnr);
389		- if (static_branch_likely(&supports_deactivate_key))
390		- gic_write_dir(irqnr);
391		-#ifdef CONFIG_SMP
392		- /*
393		- * Unlike GICv2, we don't need an smp_rmb() here.
394		- * The control dependency from gic_read_iar to
395		- * the ISB in gic_write_eoir is enough to ensure
396		- * that any shared data read by handle_IPI will
397		- * be read after the ACK.
398		- */
399		- handle_IPI(irqnr, regs);
400		-#else
401		- WARN_ONCE(true, "Unexpected SGI received!\n");
402		-#endif
403		- continue;
404		- }
405		- } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
	745	+ if (gic_prio_masking_enabled()) {
	746	+ gic_pmr_mask_irqs();
	747	+ gic_arch_enable_irqs();
	748	+ }
	749	+
	750	+ if (static_branch_likely(&supports_deactivate_key))
	751	+ gic_write_eoir(irqnr);
	752	+ else
	753	+ isb();
	754	+
	755	+ if (handle_domain_irq(gic_data.domain, irqnr, regs)) {
	756	+ WARN_ONCE(true, "Unexpected interrupt received!\n");
	757	+ log_abnormal_wakeup_reason("unexpected HW IRQ %u", irqnr);
	758	+ gic_deactivate_unhandled(irqnr);
	759	+ }
	760	+}
	761	+
	762	+static u32 gic_get_pribits(void)
	763	+{
	764	+ u32 pribits;
	765	+
	766	+ pribits = gic_read_ctlr();
	767	+ pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
	768	+ pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
	769	+ pribits++;
	770	+
	771	+ return pribits;
	772	+}
	773	+
	774	+static bool gic_has_group0(void)
	775	+{
	776	+ u32 val;
	777	+ u32 old_pmr;
	778	+
	779	+ old_pmr = gic_read_pmr();
	780	+
	781	+ /*
	782	+ * Let's find out if Group0 is under control of EL3 or not by
	783	+ * setting the highest possible, non-zero priority in PMR.
	784	+ *
	785	+ * If SCR_EL3.FIQ is set, the priority gets shifted down in
	786	+ * order for the CPU interface to set bit 7, and keep the
	787	+ * actual priority in the non-secure range. In the process, it
	788	+ * looses the least significant bit and the actual priority
	789	+ * becomes 0x80. Reading it back returns 0, indicating that
	790	+ * we're don't have access to Group0.
	791	+ */
	792	+ gic_write_pmr(BIT(8 - gic_get_pribits()));
	793	+ val = gic_read_pmr();
	794	+
	795	+ gic_write_pmr(old_pmr);
	796	+
	797	+ return val != 0;
406	798	}
407	799
408	800	static void __init gic_dist_init(void)
..	..	@@ -410,6 +802,7 @@
410	802	unsigned int i;
411	803	u64 affinity;
412	804	void __iomem *base = gic_data.dist_base;
	805	+ u32 val;
413	806
414	807	/* Disable the distributor */
415	808	writel_relaxed(0, base + GICD_CTLR);
..	..	@@ -421,22 +814,46 @@
421	814	* do the right thing if the kernel is running in secure mode,
422	815	* but that's not the intended use case anyway.
423	816	*/
424		- for (i = 32; i < gic_data.irq_nr; i += 32)
	817	+ for (i = 32; i < GIC_LINE_NR; i += 32)
425	818	writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
426	819
427		- gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
	820	+ /* Extended SPI range, not handled by the GICv2/GICv3 common code */
	821	+ for (i = 0; i < GIC_ESPI_NR; i += 32) {
	822	+ writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
	823	+ writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
	824	+ }
	825	+
	826	+ for (i = 0; i < GIC_ESPI_NR; i += 32)
	827	+ writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
	828	+
	829	+ for (i = 0; i < GIC_ESPI_NR; i += 16)
	830	+ writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
	831	+
	832	+ for (i = 0; i < GIC_ESPI_NR; i += 4)
	833	+ writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
	834	+
	835	+ /* Now do the common stuff, and wait for the distributor to drain */
	836	+ gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
	837	+
	838	+ val = GICD_CTLR_ARE_NS \| GICD_CTLR_ENABLE_G1A \| GICD_CTLR_ENABLE_G1;
	839	+ if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
	840	+ pr_info("Enabling SGIs without active state\n");
	841	+ val \|= GICD_CTLR_nASSGIreq;
	842	+ }
428	843
429	844	/* Enable distributor with ARE, Group1 */
430		- writel_relaxed(GICD_CTLR_ARE_NS \| GICD_CTLR_ENABLE_G1A \| GICD_CTLR_ENABLE_G1,
431		- base + GICD_CTLR);
	845	+ writel_relaxed(val, base + GICD_CTLR);
432	846
433	847	/*
434	848	* Set all global interrupts to the boot CPU only. ARE must be
435	849	* enabled.
436	850	*/
437	851	affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
438		- for (i = 32; i < gic_data.irq_nr; i++)
	852	+ for (i = 32; i < GIC_LINE_NR; i++)
439	853	gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
	854	+
	855	+ for (i = 0; i < GIC_ESPI_NR; i++)
	856	+ gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
440	857	}
441	858
442	859	static int gic_iterate_rdists(int (fn)(struct redist_region , void __iomem *))
..	..	@@ -496,6 +913,7 @@
496	913	typer = gic_read_typer(ptr + GICR_TYPER);
497	914	if ((typer >> 32) == aff) {
498	915	u64 offset = ptr - region->redist_base;
	916	+ raw_spin_lock_init(&gic_data_rdist()->rd_lock);
499	917	gic_data_rdist_rd_base() = ptr;
500	918	gic_data_rdist()->phys_base = region->phys_base + offset;
501	919
..	..	@@ -522,22 +940,65 @@
522	940	return -ENODEV;
523	941	}
524	942
525		-static int __gic_update_vlpi_properties(struct redist_region *region,
526		- void __iomem *ptr)
	943	+static int __gic_update_rdist_properties(struct redist_region *region,
	944	+ void __iomem *ptr)
527	945	{
528	946	u64 typer = gic_read_typer(ptr + GICR_TYPER);
	947	+
	948	+ /* Boot-time cleanip */
	949	+ if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
	950	+ u64 val;
	951	+
	952	+ /* Deactivate any present vPE */
	953	+ val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
	954	+ if (val & GICR_VPENDBASER_Valid)
	955	+ gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
	956	+ ptr + SZ_128K + GICR_VPENDBASER);
	957	+
	958	+ /* Mark the VPE table as invalid */
	959	+ val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
	960	+ val &= ~GICR_VPROPBASER_4_1_VALID;
	961	+ gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
	962	+ }
	963	+
529	964	gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
530		- gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
	965	+
	966	+ /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
	967	+ gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
	968	+ gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) \|
	969	+ gic_data.rdists.has_rvpeid);
	970	+ gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
	971	+
	972	+ /* Detect non-sensical configurations */
	973	+ if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
	974	+ gic_data.rdists.has_direct_lpi = false;
	975	+ gic_data.rdists.has_vlpis = false;
	976	+ gic_data.rdists.has_rvpeid = false;
	977	+ }
	978	+
	979	+ gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
531	980
532	981	return 1;
533	982	}
534	983
535		-static void gic_update_vlpi_properties(void)
	984	+static void gic_update_rdist_properties(void)
536	985	{
537		- gic_iterate_rdists(__gic_update_vlpi_properties);
538		- pr_info("%sVLPI support, %sdirect LPI support\n",
539		- !gic_data.rdists.has_vlpis ? "no " : "",
540		- !gic_data.rdists.has_direct_lpi ? "no " : "");
	986	+ gic_data.ppi_nr = UINT_MAX;
	987	+ gic_iterate_rdists(__gic_update_rdist_properties);
	988	+ if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
	989	+ gic_data.ppi_nr = 0;
	990	+ pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
	991	+ if (gic_data.rdists.has_vlpis)
	992	+ pr_info("GICv4 features: %s%s%s\n",
	993	+ gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
	994	+ gic_data.rdists.has_rvpeid ? "RVPEID " : "",
	995	+ gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
	996	+}
	997	+
	998	+/* Check whether it's single security state view */
	999	+static inline bool gic_dist_security_disabled(void)
	1000	+{
	1001	+ return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
541	1002	}
542	1003
543	1004	static void gic_cpu_sys_reg_init(void)
..	..	@@ -546,7 +1007,7 @@
546	1007	u64 mpidr = cpu_logical_map(cpu);
547	1008	u64 need_rss = MPIDR_RS(mpidr);
548	1009	bool group0;
549		- u32 val, pribits;
	1010	+ u32 pribits;
550	1011
551	1012	/*
552	1013	* Need to check that the SRE bit has actually been set. If
..	..	@@ -558,28 +1019,28 @@
558	1019	if (!gic_enable_sre())
559	1020	pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
560	1021
561		- pribits = gic_read_ctlr();
562		- pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
563		- pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
564		- pribits++;
	1022	+ pribits = gic_get_pribits();
565	1023
566		- /*
567		- * Let's find out if Group0 is under control of EL3 or not by
568		- * setting the highest possible, non-zero priority in PMR.
569		- *
570		- * If SCR_EL3.FIQ is set, the priority gets shifted down in
571		- * order for the CPU interface to set bit 7, and keep the
572		- * actual priority in the non-secure range. In the process, it
573		- * looses the least significant bit and the actual priority
574		- * becomes 0x80. Reading it back returns 0, indicating that
575		- * we're don't have access to Group0.
576		- */
577		- write_gicreg(BIT(8 - pribits), ICC_PMR_EL1);
578		- val = read_gicreg(ICC_PMR_EL1);
579		- group0 = val != 0;
	1024	+ group0 = gic_has_group0();
580	1025
581	1026	/* Set priority mask register */
582		- write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
	1027	+ if (!gic_prio_masking_enabled()) {
	1028	+ write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
	1029	+ } else if (gic_supports_nmi()) {
	1030	+ /*
	1031	+ * Mismatch configuration with boot CPU, the system is likely
	1032	+ * to die as interrupt masking will not work properly on all
	1033	+ * CPUs
	1034	+ *
	1035	+ * The boot CPU calls this function before enabling NMI support,
	1036	+ * and as a result we'll never see this warning in the boot path
	1037	+ * for that CPU.
	1038	+ */
	1039	+ if (static_branch_unlikely(&gic_nonsecure_priorities))
	1040	+ WARN_ON(!group0 \|\| gic_dist_security_disabled());
	1041	+ else
	1042	+ WARN_ON(group0 && !gic_dist_security_disabled());
	1043	+ }
583	1044
584	1045	/*
585	1046	* Some firmwares hand over to the kernel with the BPR changed from
..	..	@@ -604,8 +1065,10 @@
604	1065	case 7:
605	1066	write_gicreg(0, ICC_AP0R3_EL1);
606	1067	write_gicreg(0, ICC_AP0R2_EL1);
	1068	+ fallthrough;
607	1069	case 6:
608	1070	write_gicreg(0, ICC_AP0R1_EL1);
	1071	+ fallthrough;
609	1072	case 5:
610	1073	case 4:
611	1074	write_gicreg(0, ICC_AP0R0_EL1);
..	..	@@ -619,8 +1082,10 @@
619	1082	case 7:
620	1083	write_gicreg(0, ICC_AP1R3_EL1);
621	1084	write_gicreg(0, ICC_AP1R2_EL1);
	1085	+ fallthrough;
622	1086	case 6:
623	1087	write_gicreg(0, ICC_AP1R1_EL1);
	1088	+ fallthrough;
624	1089	case 5:
625	1090	case 4:
626	1091	write_gicreg(0, ICC_AP1R0_EL1);
..	..	@@ -666,12 +1131,15 @@
666	1131
667	1132	static int gic_dist_supports_lpis(void)
668	1133	{
669		- return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && !gicv3_nolpi;
	1134	+ return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
	1135	+ !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
	1136	+ !gicv3_nolpi);
670	1137	}
671	1138
672	1139	static void gic_cpu_init(void)
673	1140	{
674	1141	void __iomem *rbase;
	1142	+ int i;
675	1143
676	1144	/* Register ourselves with the rest of the world */
677	1145	if (gic_populate_rdist())
..	..	@@ -679,16 +1147,18 @@
679	1147
680	1148	gic_enable_redist(true);
681	1149
	1150	+ WARN((gic_data.ppi_nr > 16 \|\| GIC_ESPI_NR != 0) &&
	1151	+ !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
	1152	+ "Distributor has extended ranges, but CPU%d doesn't\n",
	1153	+ smp_processor_id());
	1154	+
682	1155	rbase = gic_data_rdist_sgi_base();
683	1156
684	1157	/* Configure SGIs/PPIs as non-secure Group-1 */
685		- writel_relaxed(~0, rbase + GICR_IGROUPR0);
	1158	+ for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
	1159	+ writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
686	1160
687		- gic_cpu_config(rbase, gic_redist_wait_for_rwp);
688		-
689		- /* Give LPIs a spin */
690		- if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
691		- its_cpu_init();
	1161	+ gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
692	1162
693	1163	/* initialise system registers */
694	1164	gic_cpu_sys_reg_init();
..	..	@@ -702,6 +1172,10 @@
702	1172	static int gic_starting_cpu(unsigned int cpu)
703	1173	{
704	1174	gic_cpu_init();
	1175	+
	1176	+ if (gic_dist_supports_lpis())
	1177	+ its_cpu_init();
	1178	+
705	1179	return 0;
706	1180	}
707	1181
..	..	@@ -751,11 +1225,11 @@
751	1225	gic_write_sgi1r(val);
752	1226	}
753	1227
754		-static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
	1228	+static void gic_ipi_send_mask(struct irq_data d, const struct cpumask mask)
755	1229	{
756	1230	int cpu;
757	1231
758		- if (WARN_ON(irq >= 16))
	1232	+ if (WARN_ON(d->hwirq >= 16))
759	1233	return;
760	1234
761	1235	/*
..	..	@@ -769,25 +1243,40 @@
769	1243	u16 tlist;
770	1244
771	1245	tlist = gic_compute_target_list(&cpu, mask, cluster_id);
772		- gic_send_sgi(cluster_id, tlist, irq);
	1246	+ gic_send_sgi(cluster_id, tlist, d->hwirq);
773	1247	}
774	1248
775	1249	/* Force the above writes to ICC_SGI1R_EL1 to be executed */
776	1250	isb();
777	1251	}
778	1252
779		-static void gic_smp_init(void)
	1253	+static void __init gic_smp_init(void)
780	1254	{
781		- set_smp_cross_call(gic_raise_softirq);
	1255	+ struct irq_fwspec sgi_fwspec = {
	1256	+ .fwnode = gic_data.fwnode,
	1257	+ .param_count = 1,
	1258	+ };
	1259	+ int base_sgi;
	1260	+
782	1261	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
783	1262	"irqchip/arm/gicv3:starting",
784	1263	gic_starting_cpu, NULL);
	1264	+
	1265	+ /* Register all 8 non-secure SGIs */
	1266	+ base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
	1267	+ NUMA_NO_NODE, &sgi_fwspec,
	1268	+ false, NULL);
	1269	+ if (WARN_ON(base_sgi <= 0))
	1270	+ return;
	1271	+
	1272	+ set_smp_ipi_range(base_sgi, 8);
785	1273	}
786	1274
787	1275	static int gic_set_affinity(struct irq_data d, const struct cpumask mask_val,
788	1276	bool force)
789	1277	{
790	1278	unsigned int cpu;
	1279	+ u32 offset, index;
791	1280	void __iomem *reg;
792	1281	int enabled;
793	1282	u64 val;
..	..	@@ -808,9 +1297,11 @@
808	1297	if (enabled)
809	1298	gic_mask_irq(d);
810	1299
811		- reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
	1300	+ offset = convert_offset_index(d, GICD_IROUTER, &index);
	1301	+ reg = gic_dist_base(d) + offset + (index * 8);
812	1302	val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
813	1303
	1304	+ trace_android_rvh_gic_v3_set_affinity(d, mask_val, &val, force, gic_dist_base(d));
814	1305	gic_write_irouter(val, reg);
815	1306
816	1307	/*
..	..	@@ -828,16 +1319,16 @@
828	1319	}
829	1320	#else
830	1321	#define gic_set_affinity NULL
	1322	+#define gic_ipi_send_mask NULL
831	1323	#define gic_smp_init() do { } while(0)
832	1324	#endif
833	1325
834		-#ifdef CONFIG_CPU_PM
835		-/* Check whether it's single security state view */
836		-static bool gic_dist_security_disabled(void)
	1326	+static int gic_retrigger(struct irq_data *data)
837	1327	{
838		- return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
	1328	+ return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
839	1329	}
840	1330
	1331	+#ifdef CONFIG_CPU_PM
841	1332	static int gic_cpu_pm_notifier(struct notifier_block *self,
842	1333	unsigned long cmd, void *v)
843	1334	{
..	..	@@ -865,18 +1356,41 @@
865	1356	static inline void gic_cpu_pm_init(void) { }
866	1357	#endif /* CONFIG_CPU_PM */
867	1358
	1359	+#ifdef CONFIG_PM
	1360	+void gic_resume(void)
	1361	+{
	1362	+ trace_android_vh_gic_resume(&gic_data);
	1363	+}
	1364	+EXPORT_SYMBOL_GPL(gic_resume);
	1365	+
	1366	+static struct syscore_ops gic_syscore_ops = {
	1367	+ .resume = gic_resume,
	1368	+};
	1369	+
	1370	+static void gic_syscore_init(void)
	1371	+{
	1372	+ register_syscore_ops(&gic_syscore_ops);
	1373	+}
	1374	+
	1375	+#else
	1376	+static inline void gic_syscore_init(void) { }
	1377	+void gic_resume(void) { }
	1378	+#endif
	1379	+
	1380	+
868	1381	static struct irq_chip gic_chip = {
869	1382	.name = "GICv3",
870	1383	.irq_mask = gic_mask_irq,
871	1384	.irq_unmask = gic_unmask_irq,
872	1385	.irq_eoi = gic_eoi_irq,
873	1386	.irq_set_type = gic_set_type,
874		-#ifdef CONFIG_ARCH_ROCKCHIP
875		- .irq_retrigger = gic_retrigger,
876		-#endif
877	1387	.irq_set_affinity = gic_set_affinity,
	1388	+ .irq_retrigger = gic_retrigger,
878	1389	.irq_get_irqchip_state = gic_irq_get_irqchip_state,
879	1390	.irq_set_irqchip_state = gic_irq_set_irqchip_state,
	1391	+ .irq_nmi_setup = gic_irq_nmi_setup,
	1392	+ .irq_nmi_teardown = gic_irq_nmi_teardown,
	1393	+ .ipi_send_mask = gic_ipi_send_mask,
880	1394	.flags = IRQCHIP_SET_TYPE_MASKED \|
881	1395	IRQCHIP_SKIP_SET_WAKE \|
882	1396	IRQCHIP_MASK_ON_SUSPEND,
..	..	@@ -887,71 +1401,79 @@
887	1401	.irq_mask = gic_eoimode1_mask_irq,
888	1402	.irq_unmask = gic_unmask_irq,
889	1403	.irq_eoi = gic_eoimode1_eoi_irq,
890		-#ifdef CONFIG_ARCH_ROCKCHIP
891		- .irq_retrigger = gic_retrigger,
892		-#endif
893	1404	.irq_set_type = gic_set_type,
894	1405	.irq_set_affinity = gic_set_affinity,
	1406	+ .irq_retrigger = gic_retrigger,
895	1407	.irq_get_irqchip_state = gic_irq_get_irqchip_state,
896	1408	.irq_set_irqchip_state = gic_irq_set_irqchip_state,
897	1409	.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
	1410	+ .irq_nmi_setup = gic_irq_nmi_setup,
	1411	+ .irq_nmi_teardown = gic_irq_nmi_teardown,
	1412	+ .ipi_send_mask = gic_ipi_send_mask,
898	1413	.flags = IRQCHIP_SET_TYPE_MASKED \|
899	1414	IRQCHIP_SKIP_SET_WAKE \|
900	1415	IRQCHIP_MASK_ON_SUSPEND,
901	1416	};
902	1417
903		-#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
904		-
905	1418	static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
906	1419	irq_hw_number_t hw)
907	1420	{
908	1421	struct irq_chip *chip = &gic_chip;
	1422	+ struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
909	1423
910	1424	if (static_branch_likely(&supports_deactivate_key))
911	1425	chip = &gic_eoimode1_chip;
912	1426
913		- /* SGIs are private to the core kernel */
914		- if (hw < 16)
915		- return -EPERM;
916		- /* Nothing here */
917		- if (hw >= gic_data.irq_nr && hw < 8192)
918		- return -EPERM;
919		- /* Off limits */
920		- if (hw >= GIC_ID_NR)
921		- return -EPERM;
	1427	+ switch (__get_intid_range(hw)) {
	1428	+ case SGI_RANGE:
	1429	+ irq_set_percpu_devid(irq);
	1430	+ irq_domain_set_info(d, irq, hw, chip, d->host_data,
	1431	+ handle_percpu_devid_fasteoi_ipi,
	1432	+ NULL, NULL);
	1433	+ break;
922	1434
923		- /* PPIs */
924		- if (hw < 32) {
	1435	+ case PPI_RANGE:
	1436	+ case EPPI_RANGE:
925	1437	irq_set_percpu_devid(irq);
926	1438	irq_domain_set_info(d, irq, hw, chip, d->host_data,
927	1439	handle_percpu_devid_irq, NULL, NULL);
928		- irq_set_status_flags(irq, IRQ_NOAUTOEN);
929		- }
930		- /* SPIs */
931		- if (hw >= 32 && hw < gic_data.irq_nr) {
	1440	+ break;
	1441	+
	1442	+ case SPI_RANGE:
	1443	+ case ESPI_RANGE:
932	1444	irq_domain_set_info(d, irq, hw, chip, d->host_data,
933	1445	handle_fasteoi_irq, NULL, NULL);
934	1446	irq_set_probe(irq);
935		- irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
936		- }
937		- /* LPIs */
938		- if (hw >= 8192 && hw < GIC_ID_NR) {
	1447	+ irqd_set_single_target(irqd);
	1448	+ break;
	1449	+
	1450	+ case LPI_RANGE:
939	1451	if (!gic_dist_supports_lpis())
940	1452	return -EPERM;
941	1453	irq_domain_set_info(d, irq, hw, chip, d->host_data,
942	1454	handle_fasteoi_irq, NULL, NULL);
	1455	+ break;
	1456	+
	1457	+ default:
	1458	+ return -EPERM;
943	1459	}
944	1460
	1461	+ /* Prevents SW retriggers which mess up the ACK/EOI ordering */
	1462	+ irqd_set_handle_enforce_irqctx(irqd);
945	1463	return 0;
946	1464	}
947		-
948		-#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
949	1465
950	1466	static int gic_irq_domain_translate(struct irq_domain *d,
951	1467	struct irq_fwspec *fwspec,
952	1468	unsigned long *hwirq,
953	1469	unsigned int *type)
954	1470	{
	1471	+ if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
	1472	+ *hwirq = fwspec->param[0];
	1473	+ *type = IRQ_TYPE_EDGE_RISING;
	1474	+ return 0;
	1475	+ }
	1476	+
955	1477	if (is_of_node(fwspec->fwnode)) {
956	1478	if (fwspec->param_count < 3)
957	1479	return -EINVAL;
..	..	@@ -961,11 +1483,23 @@
961	1483	*hwirq = fwspec->param[1] + 32;
962	1484	break;
963	1485	case 1: /* PPI */
964		- case GIC_IRQ_TYPE_PARTITION:
965	1486	*hwirq = fwspec->param[1] + 16;
	1487	+ break;
	1488	+ case 2: /* ESPI */
	1489	+ *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
	1490	+ break;
	1491	+ case 3: /* EPPI */
	1492	+ *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
966	1493	break;
967	1494	case GIC_IRQ_TYPE_LPI: /* LPI */
968	1495	*hwirq = fwspec->param[1];
	1496	+ break;
	1497	+ case GIC_IRQ_TYPE_PARTITION:
	1498	+ *hwirq = fwspec->param[1];
	1499	+ if (fwspec->param[1] >= 16)
	1500	+ *hwirq += EPPI_BASE_INTID - 16;
	1501	+ else
	1502	+ *hwirq += 16;
969	1503	break;
970	1504	default:
971	1505	return -EINVAL;
..	..	@@ -975,7 +1509,7 @@
975	1509
976	1510	/*
977	1511	* Make it clear that broken DTs are... broken.
978		- * Partitionned PPIs are an unfortunate exception.
	1512	+ * Partitioned PPIs are an unfortunate exception.
979	1513	*/
980	1514	WARN_ON(*type == IRQ_TYPE_NONE &&
981	1515	fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
..	..	@@ -985,6 +1519,12 @@
985	1519	if (is_fwnode_irqchip(fwspec->fwnode)) {
986	1520	if(fwspec->param_count != 2)
987	1521	return -EINVAL;
	1522	+
	1523	+ if (fwspec->param[0] < 16) {
	1524	+ pr_err(FW_BUG "Illegal GSI%d translation request\n",
	1525	+ fwspec->param[0]);
	1526	+ return -EINVAL;
	1527	+ }
988	1528
989	1529	*hwirq = fwspec->param[0];
990	1530	*type = fwspec->param[1];
..	..	@@ -1046,7 +1586,8 @@
1046	1586	* then we need to match the partition domain.
1047	1587	*/
1048	1588	if (fwspec->param_count >= 4 &&
1049		- fwspec->param[0] == 1 && fwspec->param[3] != 0)
	1589	+ fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
	1590	+ gic_data.ppi_descs)
1050	1591	return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1051	1592
1052	1593	return d == gic_data.domain;
..	..	@@ -1066,6 +1607,9 @@
1066	1607	{
1067	1608	struct device_node *np;
1068	1609	int ret;
	1610	+
	1611	+ if (!gic_data.ppi_descs)
	1612	+ return -ENOMEM;
1069	1613
1070	1614	np = of_find_node_by_phandle(fwspec->param[3]);
1071	1615	if (WARN_ON(!np))
..	..	@@ -1087,6 +1631,186 @@
1087	1631	.select = gic_irq_domain_select,
1088	1632	};
1089	1633
	1634	+static bool gic_enable_quirk_msm8996(void *data)
	1635	+{
	1636	+ struct gic_chip_data *d = data;
	1637	+
	1638	+ d->flags \|= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
	1639	+
	1640	+ return true;
	1641	+}
	1642	+
	1643	+static bool gic_enable_quirk_mtk_gicr(void *data)
	1644	+{
	1645	+ struct gic_chip_data *d = data;
	1646	+
	1647	+ d->flags \|= FLAGS_WORKAROUND_MTK_GICR_SAVE;
	1648	+
	1649	+ return true;
	1650	+}
	1651	+
	1652	+static bool gic_enable_quirk_cavium_38539(void *data)
	1653	+{
	1654	+ struct gic_chip_data *d = data;
	1655	+
	1656	+ d->flags \|= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
	1657	+
	1658	+ return true;
	1659	+}
	1660	+
	1661	+static bool gic_enable_quirk_hip06_07(void *data)
	1662	+{
	1663	+ struct gic_chip_data *d = data;
	1664	+
	1665	+ /*
	1666	+ * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
	1667	+ * not being an actual ARM implementation). The saving grace is
	1668	+ * that GIC-600 doesn't have ESPI, so nothing to do in that case.
	1669	+ * HIP07 doesn't even have a proper IIDR, and still pretends to
	1670	+ * have ESPI. In both cases, put them right.
	1671	+ */
	1672	+ if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
	1673	+ /* Zero both ESPI and the RES0 field next to it... */
	1674	+ d->rdists.gicd_typer &= ~GENMASK(9, 8);
	1675	+ return true;
	1676	+ }
	1677	+
	1678	+ return false;
	1679	+}
	1680	+
	1681	+static bool gic_enable_quirk_arm64_2941627(void *data)
	1682	+{
	1683	+ static_branch_enable(&gic_arm64_2941627_erratum);
	1684	+ return true;
	1685	+}
	1686	+
	1687	+static const struct gic_quirk gic_quirks[] = {
	1688	+ {
	1689	+ .desc = "GICv3: Qualcomm MSM8996 broken firmware",
	1690	+ .compatible = "qcom,msm8996-gic-v3",
	1691	+ .init = gic_enable_quirk_msm8996,
	1692	+ },
	1693	+ {
	1694	+ .desc = "GICv3: Mediatek Chromebook GICR save problem",
	1695	+ .property = "mediatek,broken-save-restore-fw",
	1696	+ .init = gic_enable_quirk_mtk_gicr,
	1697	+ },
	1698	+ {
	1699	+ .desc = "GICv3: HIP06 erratum 161010803",
	1700	+ .iidr = 0x0204043b,
	1701	+ .mask = 0xffffffff,
	1702	+ .init = gic_enable_quirk_hip06_07,
	1703	+ },
	1704	+ {
	1705	+ .desc = "GICv3: HIP07 erratum 161010803",
	1706	+ .iidr = 0x00000000,
	1707	+ .mask = 0xffffffff,
	1708	+ .init = gic_enable_quirk_hip06_07,
	1709	+ },
	1710	+ {
	1711	+ /*
	1712	+ * Reserved register accesses generate a Synchronous
	1713	+ * External Abort. This erratum applies to:
	1714	+ * - ThunderX: CN88xx
	1715	+ * - OCTEON TX: CN83xx, CN81xx
	1716	+ * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
	1717	+ */
	1718	+ .desc = "GICv3: Cavium erratum 38539",
	1719	+ .iidr = 0xa000034c,
	1720	+ .mask = 0xe8f00fff,
	1721	+ .init = gic_enable_quirk_cavium_38539,
	1722	+ },
	1723	+ {
	1724	+ /*
	1725	+ * GIC-700: 2941627 workaround - IP variant [0,1]
	1726	+ *
	1727	+ */
	1728	+ .desc = "GICv3: ARM64 erratum 2941627",
	1729	+ .iidr = 0x0400043b,
	1730	+ .mask = 0xff0e0fff,
	1731	+ .init = gic_enable_quirk_arm64_2941627,
	1732	+ },
	1733	+ {
	1734	+ /*
	1735	+ * GIC-700: 2941627 workaround - IP variant [2]
	1736	+ */
	1737	+ .desc = "GICv3: ARM64 erratum 2941627",
	1738	+ .iidr = 0x0402043b,
	1739	+ .mask = 0xff0f0fff,
	1740	+ .init = gic_enable_quirk_arm64_2941627,
	1741	+ },
	1742	+ {
	1743	+ }
	1744	+};
	1745	+
	1746	+static void gic_enable_nmi_support(void)
	1747	+{
	1748	+ int i;
	1749	+
	1750	+ if (!gic_prio_masking_enabled())
	1751	+ return;
	1752	+
	1753	+ if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) {
	1754	+ pr_warn("Skipping NMI enable due to firmware issues\n");
	1755	+ return;
	1756	+ }
	1757	+
	1758	+ ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
	1759	+ if (!ppi_nmi_refs)
	1760	+ return;
	1761	+
	1762	+ for (i = 0; i < gic_data.ppi_nr; i++)
	1763	+ refcount_set(&ppi_nmi_refs[i], 0);
	1764	+
	1765	+ /*
	1766	+ * Linux itself doesn't use 1:N distribution, so has no need to
	1767	+ * set PMHE. The only reason to have it set is if EL3 requires it
	1768	+ * (and we can't change it).
	1769	+ */
	1770	+ if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
	1771	+ static_branch_enable(&gic_pmr_sync);
	1772	+
	1773	+ pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
	1774	+ static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
	1775	+
	1776	+ /*
	1777	+ * How priority values are used by the GIC depends on two things:
	1778	+ * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
	1779	+ * and if Group 0 interrupts can be delivered to Linux in the non-secure
	1780	+ * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
	1781	+ * the ICC_PMR_EL1 register and the priority that software assigns to
	1782	+ * interrupts:
	1783	+ *
	1784	+ * GICD_CTRL.DS \| SCR_EL3.FIQ \| ICC_PMR_EL1 \| Group 1 priority
	1785	+ * -----------------------------------------------------------
	1786	+ * 1 \| - \| unchanged \| unchanged
	1787	+ * -----------------------------------------------------------
	1788	+ * 0 \| 1 \| non-secure \| non-secure
	1789	+ * -----------------------------------------------------------
	1790	+ * 0 \| 0 \| unchanged \| non-secure
	1791	+ *
	1792	+ * where non-secure means that the value is right-shifted by one and the
	1793	+ * MSB bit set, to make it fit in the non-secure priority range.
	1794	+ *
	1795	+ * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
	1796	+ * are both either modified or unchanged, we can use the same set of
	1797	+ * priorities.
	1798	+ *
	1799	+ * In the last case, where only the interrupt priorities are modified to
	1800	+ * be in the non-secure range, we use a different PMR value to mask IRQs
	1801	+ * and the rest of the values that we use remain unchanged.
	1802	+ */
	1803	+ if (gic_has_group0() && !gic_dist_security_disabled())
	1804	+ static_branch_enable(&gic_nonsecure_priorities);
	1805	+
	1806	+ static_branch_enable(&supports_pseudo_nmis);
	1807	+
	1808	+ if (static_branch_likely(&supports_deactivate_key))
	1809	+ gic_eoimode1_chip.flags \|= IRQCHIP_SUPPORTS_NMI;
	1810	+ else
	1811	+ gic_chip.flags \|= IRQCHIP_SUPPORTS_NMI;
	1812	+}
	1813	+
1090	1814	static int __init gic_init_bases(void __iomem *dist_base,
1091	1815	struct redist_region *rdist_regs,
1092	1816	u32 nr_redist_regions,
..	..	@@ -1094,7 +1818,6 @@
1094	1818	struct fwnode_handle *handle)
1095	1819	{
1096	1820	u32 typer;
1097		- int gic_irqs;
1098	1821	int err;
1099	1822
1100	1823	if (!is_hyp_mode_available())
..	..	@@ -1111,26 +1834,37 @@
1111	1834
1112	1835	/*
1113	1836	* Find out how many interrupts are supported.
1114		- * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1115	1837	*/
1116	1838	typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1117	1839	gic_data.rdists.gicd_typer = typer;
1118		- gic_irqs = GICD_TYPER_IRQS(typer);
1119		- if (gic_irqs > 1020)
1120		- gic_irqs = 1020;
1121		- gic_data.irq_nr = gic_irqs;
	1840	+
	1841	+ gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
	1842	+ gic_quirks, &gic_data);
	1843	+
	1844	+ pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
	1845	+ pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
	1846	+
	1847	+ /*
	1848	+ * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
	1849	+ * architecture spec (which says that reserved registers are RES0).
	1850	+ */
	1851	+ if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
	1852	+ gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1122	1853
1123	1854	gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1124	1855	&gic_data);
1125		- irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1126	1856	gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
	1857	+ gic_data.rdists.has_rvpeid = true;
1127	1858	gic_data.rdists.has_vlpis = true;
1128	1859	gic_data.rdists.has_direct_lpi = true;
	1860	+ gic_data.rdists.has_vpend_valid_dirty = true;
1129	1861
1130	1862	if (WARN_ON(!gic_data.domain) \|\| WARN_ON(!gic_data.rdists.rdist)) {
1131	1863	err = -ENOMEM;
1132	1864	goto out_free;
1133	1865	}
	1866	+
	1867	+ irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1134	1868
1135	1869	gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1136	1870	pr_info("Distributor has %sRange Selector support\n",
..	..	@@ -1144,15 +1878,23 @@
1144	1878
1145	1879	set_handle_irq(gic_handle_irq);
1146	1880
1147		- gic_update_vlpi_properties();
	1881	+ gic_update_rdist_properties();
1148	1882
1149		- if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
1150		- its_init(handle, &gic_data.rdists, gic_data.domain);
1151		-
1152		- gic_smp_init();
1153	1883	gic_dist_init();
1154	1884	gic_cpu_init();
	1885	+ gic_smp_init();
1155	1886	gic_cpu_pm_init();
	1887	+ gic_syscore_init();
	1888	+
	1889	+ if (gic_dist_supports_lpis()) {
	1890	+ its_init(handle, &gic_data.rdists, gic_data.domain);
	1891	+ its_cpu_init();
	1892	+ } else {
	1893	+ if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
	1894	+ gicv2m_init(handle, gic_data.domain);
	1895	+ }
	1896	+
	1897	+ gic_enable_nmi_support();
1156	1898
1157	1899	return 0;
1158	1900
..	..	@@ -1185,6 +1927,10 @@
1185	1927	if (!parts_node)
1186	1928	return;
1187	1929
	1930	+ gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
	1931	+ if (!gic_data.ppi_descs)
	1932	+ goto out_put_node;
	1933	+
1188	1934	nr_parts = of_get_child_count(parts_node);
1189	1935
1190	1936	if (!nr_parts)
..	..	@@ -1202,8 +1948,8 @@
1202	1948
1203	1949	part->partition_id = of_node_to_fwnode(child_part);
1204	1950
1205		- pr_info("GIC: PPI partition %s[%d] { ",
1206		- child_part->name, part_idx);
	1951	+ pr_info("GIC: PPI partition %pOFn[%d] { ",
	1952	+ child_part, part_idx);
1207	1953
1208	1954	n = of_property_count_elems_of_size(child_part, "affinity",
1209	1955	sizeof(u32));
..	..	@@ -1224,19 +1970,22 @@
1224	1970	continue;
1225	1971
1226	1972	cpu = of_cpu_node_to_id(cpu_node);
1227		- if (WARN_ON(cpu < 0))
	1973	+ if (WARN_ON(cpu < 0)) {
	1974	+ of_node_put(cpu_node);
1228	1975	continue;
	1976	+ }
1229	1977
1230	1978	pr_cont("%pOF[%d] ", cpu_node, cpu);
1231	1979
1232	1980	cpumask_set_cpu(cpu, &part->mask);
	1981	+ of_node_put(cpu_node);
1233	1982	}
1234	1983
1235	1984	pr_cont("}\n");
1236	1985	part_idx++;
1237	1986	}
1238	1987
1239		- for (i = 0; i < 16; i++) {
	1988	+ for (i = 0; i < gic_data.ppi_nr; i++) {
1240	1989	unsigned int irq;
1241	1990	struct partition_desc *desc;
1242	1991	struct irq_fwspec ppi_fwspec = {
..	..	@@ -1286,10 +2035,11 @@
1286	2035	gic_v3_kvm_info.vcpu = r;
1287	2036
1288	2037	gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
	2038	+ gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
1289	2039	gic_set_kvm_info(&gic_v3_kvm_info);
1290	2040	}
1291	2041
1292		-static int __init gicv3_of_init(struct device_node node, struct device_node parent)
	2042	+static int __init gic_of_init(struct device_node node, struct device_node parent)
1293	2043	{
1294	2044	void __iomem *dist_base;
1295	2045	struct redist_region *rdist_regs;
..	..	@@ -1336,6 +2086,8 @@
1336	2086	if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1337	2087	redist_stride = 0;
1338	2088
	2089	+ gic_enable_of_quirks(node, gic_quirks, &gic_data);
	2090	+
1339	2091	err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1340	2092	redist_stride, &node->fwnode);
1341	2093	if (err)
..	..	@@ -1357,7 +2109,7 @@
1357	2109	return err;
1358	2110	}
1359	2111
1360		-IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gicv3_of_init);
	2112	+IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1361	2113
1362	2114	#ifdef CONFIG_ACPI
1363	2115	static struct
..	..	@@ -1384,7 +2136,7 @@
1384	2136	}
1385	2137
1386	2138	static int __init
1387		-gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
	2139	+gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
1388	2140	const unsigned long end)
1389	2141	{
1390	2142	struct acpi_madt_generic_redistributor *redist =
..	..	@@ -1402,7 +2154,7 @@
1402	2154	}
1403	2155
1404	2156	static int __init
1405		-gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
	2157	+gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
1406	2158	const unsigned long end)
1407	2159	{
1408	2160	struct acpi_madt_generic_interrupt *gicc =
..	..	@@ -1444,14 +2196,14 @@
1444	2196	return -ENODEV;
1445	2197	}
1446	2198
1447		-static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
	2199	+static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
1448	2200	const unsigned long end)
1449	2201	{
1450	2202	/* Subtable presence means that redist exists, that's it */
1451	2203	return 0;
1452	2204	}
1453	2205
1454		-static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
	2206	+static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
1455	2207	const unsigned long end)
1456	2208	{
1457	2209	struct acpi_madt_generic_interrupt *gicc =
..	..	@@ -1521,7 +2273,7 @@
1521	2273	return true;
1522	2274	}
1523	2275
1524		-static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header,
	2276	+static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
1525	2277	const unsigned long end)
1526	2278	{
1527	2279	struct acpi_madt_generic_interrupt *gicc =
..	..	@@ -1599,11 +2351,12 @@
1599	2351	}
1600	2352
1601	2353	gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
	2354	+ gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
1602	2355	gic_set_kvm_info(&gic_v3_kvm_info);
1603	2356	}
1604	2357
1605	2358	static int __init
1606		-gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
	2359	+gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
1607	2360	{
1608	2361	struct acpi_madt_generic_distributor *dist;
1609	2362	struct fwnode_handle *domain_handle;
..	..	@@ -1637,7 +2390,7 @@
1637	2390	if (err)
1638	2391	goto out_redist_unmap;
1639	2392
1640		- domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
	2393	+ domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1641	2394	if (!domain_handle) {
1642	2395	err = -ENOMEM;
1643	2396	goto out_redist_unmap;