| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Generic Broadcom Set Top Box Level 2 Interrupt controller driver |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2014-2017 Broadcom |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License version 2 as |
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| 8 | | - * published by the Free Software Foundation. |
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| 9 | | - * |
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| 10 | | - * This program is distributed in the hope that it will be useful, |
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| 11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 13 | | - * GNU General Public License for more details. |
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| 14 | 6 | */ |
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| 15 | 7 | |
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| 16 | 8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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| .. | .. |
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| 169 | 161 | *init_params) |
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| 170 | 162 | { |
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| 171 | 163 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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| 164 | + unsigned int set = 0; |
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| 172 | 165 | struct brcmstb_l2_intc_data *data; |
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| 173 | 166 | struct irq_chip_type *ct; |
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| 174 | 167 | int ret; |
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| .. | .. |
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| 216 | 209 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
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| 217 | 210 | flags |= IRQ_GC_BE_IO; |
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| 218 | 211 | |
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| 212 | + if (init_params->handler == handle_level_irq) |
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| 213 | + set |= IRQ_LEVEL; |
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| 214 | + |
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| 219 | 215 | /* Allocate a single Generic IRQ chip for this node */ |
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| 220 | 216 | ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, |
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| 221 | | - np->full_name, init_params->handler, clr, 0, flags); |
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| 217 | + np->full_name, init_params->handler, clr, set, flags); |
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| 222 | 218 | if (ret) { |
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| 223 | 219 | pr_err("failed to allocate generic irq chip\n"); |
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| 224 | 220 | goto out_free_domain; |
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| .. | .. |
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| 262 | 258 | */ |
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| 263 | 259 | data->gc->wake_enabled = 0xffffffff; |
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| 264 | 260 | ct->chip.irq_set_wake = irq_gc_set_wake; |
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| 261 | + enable_irq_wake(parent_irq); |
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| 265 | 262 | } |
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| 263 | + |
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| 264 | + pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq); |
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| 266 | 265 | |
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| 267 | 266 | return 0; |
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| 268 | 267 | |
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| .. | .. |
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| 275 | 274 | return ret; |
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| 276 | 275 | } |
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| 277 | 276 | |
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| 278 | | -int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, |
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| 277 | +static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, |
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| 279 | 278 | struct device_node *parent) |
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| 280 | 279 | { |
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| 281 | 280 | return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); |
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| 282 | 281 | } |
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| 283 | 282 | IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init); |
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| 283 | +IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc", |
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| 284 | + brcmstb_l2_edge_intc_of_init); |
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| 285 | +IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc", |
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| 286 | + brcmstb_l2_edge_intc_of_init); |
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| 284 | 287 | |
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| 285 | | -int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, |
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| 288 | +static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, |
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| 286 | 289 | struct device_node *parent) |
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| 287 | 290 | { |
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| 288 | 291 | return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); |
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