| .. | .. |
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| 15 | 15 | #include <linux/kernel.h> |
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| 16 | 16 | #include <linux/module.h> |
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| 17 | 17 | #include <linux/moduleparam.h> |
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| 18 | +#include <linux/mutex.h> |
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| 18 | 19 | #include <linux/spinlock.h> |
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| 20 | +#include <linux/types.h> |
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| 19 | 21 | |
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| 20 | 22 | #define STX104_OUT_CHAN(chan) { \ |
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| 21 | 23 | .type = IIO_VOLTAGE, \ |
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| .. | .. |
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| 45 | 47 | MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); |
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| 46 | 48 | |
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| 47 | 49 | /** |
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| 50 | + * struct stx104_reg - device register structure |
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| 51 | + * @ssr_ad: Software Strobe Register and ADC Data |
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| 52 | + * @achan: ADC Channel |
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| 53 | + * @dio: Digital I/O |
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| 54 | + * @dac: DAC Channels |
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| 55 | + * @cir_asr: Clear Interrupts and ADC Status |
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| 56 | + * @acr: ADC Control |
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| 57 | + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB |
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| 58 | + * @acfg: ADC Configuration |
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| 59 | + */ |
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| 60 | +struct stx104_reg { |
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| 61 | + u16 ssr_ad; |
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| 62 | + u8 achan; |
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| 63 | + u8 dio; |
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| 64 | + u16 dac[2]; |
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| 65 | + u8 cir_asr; |
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| 66 | + u8 acr; |
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| 67 | + u8 pccr_fsh; |
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| 68 | + u8 acfg; |
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| 69 | +}; |
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| 70 | + |
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| 71 | +/** |
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| 48 | 72 | * struct stx104_iio - IIO device private data structure |
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| 73 | + * @lock: synchronization lock to prevent I/O race conditions |
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| 49 | 74 | * @chan_out_states: channels' output states |
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| 50 | | - * @base: base port address of the IIO device |
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| 75 | + * @reg: I/O address offset for the device registers |
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| 51 | 76 | */ |
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| 52 | 77 | struct stx104_iio { |
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| 78 | + struct mutex lock; |
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| 53 | 79 | unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; |
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| 54 | | - unsigned int base; |
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| 80 | + struct stx104_reg __iomem *reg; |
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| 55 | 81 | }; |
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| 56 | 82 | |
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| 57 | 83 | /** |
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| .. | .. |
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| 64 | 90 | struct stx104_gpio { |
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| 65 | 91 | struct gpio_chip chip; |
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| 66 | 92 | spinlock_t lock; |
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| 67 | | - unsigned int base; |
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| 93 | + u8 __iomem *base; |
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| 68 | 94 | unsigned int out_state; |
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| 69 | 95 | }; |
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| 70 | 96 | |
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| .. | .. |
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| 72 | 98 | struct iio_chan_spec const *chan, int *val, int *val2, long mask) |
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| 73 | 99 | { |
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| 74 | 100 | struct stx104_iio *const priv = iio_priv(indio_dev); |
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| 101 | + struct stx104_reg __iomem *const reg = priv->reg; |
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| 75 | 102 | unsigned int adc_config; |
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| 76 | 103 | int adbu; |
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| 77 | 104 | int gain; |
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| .. | .. |
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| 79 | 106 | switch (mask) { |
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| 80 | 107 | case IIO_CHAN_INFO_HARDWAREGAIN: |
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| 81 | 108 | /* get gain configuration */ |
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| 82 | | - adc_config = inb(priv->base + 11); |
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| 109 | + adc_config = ioread8(®->acfg); |
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| 83 | 110 | gain = adc_config & 0x3; |
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| 84 | 111 | |
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| 85 | 112 | *val = 1 << gain; |
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| .. | .. |
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| 90 | 117 | return IIO_VAL_INT; |
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| 91 | 118 | } |
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| 92 | 119 | |
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| 120 | + mutex_lock(&priv->lock); |
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| 121 | + |
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| 93 | 122 | /* select ADC channel */ |
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| 94 | | - outb(chan->channel | (chan->channel << 4), priv->base + 2); |
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| 123 | + iowrite8(chan->channel | (chan->channel << 4), ®->achan); |
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| 95 | 124 | |
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| 96 | | - /* trigger ADC sample capture and wait for completion */ |
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| 97 | | - outb(0, priv->base); |
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| 98 | | - while (inb(priv->base + 8) & BIT(7)); |
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| 125 | + /* trigger ADC sample capture by writing to the 8-bit |
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| 126 | + * Software Strobe Register and wait for completion |
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| 127 | + */ |
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| 128 | + iowrite8(0, ®->ssr_ad); |
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| 129 | + while (ioread8(®->cir_asr) & BIT(7)); |
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| 99 | 130 | |
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| 100 | | - *val = inw(priv->base); |
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| 131 | + *val = ioread16(®->ssr_ad); |
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| 132 | + |
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| 133 | + mutex_unlock(&priv->lock); |
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| 101 | 134 | return IIO_VAL_INT; |
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| 102 | 135 | case IIO_CHAN_INFO_OFFSET: |
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| 103 | 136 | /* get ADC bipolar/unipolar configuration */ |
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| 104 | | - adc_config = inb(priv->base + 11); |
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| 137 | + adc_config = ioread8(®->acfg); |
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| 105 | 138 | adbu = !(adc_config & BIT(2)); |
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| 106 | 139 | |
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| 107 | 140 | *val = -32768 * adbu; |
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| 108 | 141 | return IIO_VAL_INT; |
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| 109 | 142 | case IIO_CHAN_INFO_SCALE: |
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| 110 | 143 | /* get ADC bipolar/unipolar and gain configuration */ |
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| 111 | | - adc_config = inb(priv->base + 11); |
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| 144 | + adc_config = ioread8(®->acfg); |
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| 112 | 145 | adbu = !(adc_config & BIT(2)); |
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| 113 | 146 | gain = adc_config & 0x3; |
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| 114 | 147 | |
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| .. | .. |
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| 130 | 163 | /* Only four gain states (x1, x2, x4, x8) */ |
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| 131 | 164 | switch (val) { |
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| 132 | 165 | case 1: |
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| 133 | | - outb(0, priv->base + 11); |
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| 166 | + iowrite8(0, &priv->reg->acfg); |
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| 134 | 167 | break; |
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| 135 | 168 | case 2: |
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| 136 | | - outb(1, priv->base + 11); |
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| 169 | + iowrite8(1, &priv->reg->acfg); |
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| 137 | 170 | break; |
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| 138 | 171 | case 4: |
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| 139 | | - outb(2, priv->base + 11); |
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| 172 | + iowrite8(2, &priv->reg->acfg); |
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| 140 | 173 | break; |
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| 141 | 174 | case 8: |
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| 142 | | - outb(3, priv->base + 11); |
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| 175 | + iowrite8(3, &priv->reg->acfg); |
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| 143 | 176 | break; |
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| 144 | 177 | default: |
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| 145 | 178 | return -EINVAL; |
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| .. | .. |
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| 152 | 185 | if ((unsigned int)val > 65535) |
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| 153 | 186 | return -EINVAL; |
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| 154 | 187 | |
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| 155 | | - priv->chan_out_states[chan->channel] = val; |
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| 156 | | - outw(val, priv->base + 4 + 2 * chan->channel); |
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| 188 | + mutex_lock(&priv->lock); |
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| 157 | 189 | |
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| 190 | + priv->chan_out_states[chan->channel] = val; |
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| 191 | + iowrite16(val, &priv->reg->dac[chan->channel]); |
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| 192 | + |
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| 193 | + mutex_unlock(&priv->lock); |
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| 158 | 194 | return 0; |
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| 159 | 195 | } |
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| 160 | 196 | return -EINVAL; |
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| .. | .. |
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| 222 | 258 | if (offset >= 4) |
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| 223 | 259 | return -EINVAL; |
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| 224 | 260 | |
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| 225 | | - return !!(inb(stx104gpio->base) & BIT(offset)); |
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| 261 | + return !!(ioread8(stx104gpio->base) & BIT(offset)); |
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| 226 | 262 | } |
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| 227 | 263 | |
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| 228 | 264 | static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
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| .. | .. |
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| 230 | 266 | { |
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| 231 | 267 | struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); |
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| 232 | 268 | |
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| 233 | | - *bits = inb(stx104gpio->base); |
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| 269 | + *bits = ioread8(stx104gpio->base); |
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| 234 | 270 | |
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| 235 | 271 | return 0; |
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| 236 | 272 | } |
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| .. | .. |
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| 252 | 288 | else |
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| 253 | 289 | stx104gpio->out_state &= ~mask; |
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| 254 | 290 | |
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| 255 | | - outb(stx104gpio->out_state, stx104gpio->base); |
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| 291 | + iowrite8(stx104gpio->out_state, stx104gpio->base); |
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| 256 | 292 | |
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| 257 | 293 | spin_unlock_irqrestore(&stx104gpio->lock, flags); |
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| 258 | 294 | } |
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| .. | .. |
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| 279 | 315 | |
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| 280 | 316 | stx104gpio->out_state &= ~*mask; |
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| 281 | 317 | stx104gpio->out_state |= *mask & *bits; |
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| 282 | | - outb(stx104gpio->out_state, stx104gpio->base); |
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| 318 | + iowrite8(stx104gpio->out_state, stx104gpio->base); |
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| 283 | 319 | |
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| 284 | 320 | spin_unlock_irqrestore(&stx104gpio->lock, flags); |
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| 285 | 321 | } |
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| .. | .. |
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| 306 | 342 | return -EBUSY; |
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| 307 | 343 | } |
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| 308 | 344 | |
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| 345 | + priv = iio_priv(indio_dev); |
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| 346 | + priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT); |
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| 347 | + if (!priv->reg) |
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| 348 | + return -ENOMEM; |
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| 349 | + |
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| 309 | 350 | indio_dev->info = &stx104_info; |
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| 310 | 351 | indio_dev->modes = INDIO_DIRECT_MODE; |
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| 311 | 352 | |
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| 312 | 353 | /* determine if differential inputs */ |
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| 313 | | - if (inb(base[id] + 8) & BIT(5)) { |
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| 354 | + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { |
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| 314 | 355 | indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); |
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| 315 | 356 | indio_dev->channels = stx104_channels_diff; |
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| 316 | 357 | } else { |
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| .. | .. |
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| 320 | 361 | |
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| 321 | 362 | indio_dev->name = dev_name(dev); |
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| 322 | 363 | |
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| 323 | | - priv = iio_priv(indio_dev); |
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| 324 | | - priv->base = base[id]; |
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| 364 | + mutex_init(&priv->lock); |
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| 325 | 365 | |
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| 326 | 366 | /* configure device for software trigger operation */ |
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| 327 | | - outb(0, base[id] + 9); |
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| 367 | + iowrite8(0, &priv->reg->acr); |
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| 328 | 368 | |
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| 329 | 369 | /* initialize gain setting to x1 */ |
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| 330 | | - outb(0, base[id] + 11); |
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| 370 | + iowrite8(0, &priv->reg->acfg); |
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| 331 | 371 | |
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| 332 | 372 | /* initialize DAC output to 0V */ |
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| 333 | | - outw(0, base[id] + 4); |
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| 334 | | - outw(0, base[id] + 6); |
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| 373 | + iowrite16(0, &priv->reg->dac[0]); |
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| 374 | + iowrite16(0, &priv->reg->dac[1]); |
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| 335 | 375 | |
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| 336 | 376 | stx104gpio->chip.label = dev_name(dev); |
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| 337 | 377 | stx104gpio->chip.parent = dev; |
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| .. | .. |
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| 346 | 386 | stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; |
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| 347 | 387 | stx104gpio->chip.set = stx104_gpio_set; |
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| 348 | 388 | stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; |
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| 349 | | - stx104gpio->base = base[id] + 3; |
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| 389 | + stx104gpio->base = &priv->reg->dio; |
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| 350 | 390 | stx104gpio->out_state = 0x0; |
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| 351 | 391 | |
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| 352 | 392 | spin_lock_init(&stx104gpio->lock); |
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