~hc/RK356X_SDK_RELEASE.git

..	..	@@ -14,27 +14,43 @@
14	14	#include <linux/irqchip/chained_irq.h>
15	15	#include <linux/irqdesc.h>
16	16	#include <linux/irqdomain.h>
	17	+#include <linux/mfd/syscon.h>
17	18	#include <linux/module.h>
18	19	#include <linux/of_device.h>
	20	+#include <linux/pm_runtime.h>
	21	+#include <linux/regmap.h>
19	22	#include <linux/regulator/consumer.h>
20	23	#include <linux/slab.h>
21	24
22	25	#include "stm32-adc-core.h"
23	26
	27	+#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
	28	+
	29	+/* SYSCFG registers */
	30	+#define STM32MP1_SYSCFG_PMCSETR 0x04
	31	+#define STM32MP1_SYSCFG_PMCCLRR 0x44
	32	+
	33	+/* SYSCFG bit fields */
	34	+#define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
	35	+
	36	+/* SYSCFG capability flags */
	37	+#define HAS_VBOOSTER BIT(0)
	38	+#define HAS_ANASWVDD BIT(1)
	39	+
24	40	/**
25		- * stm32_adc_common_regs - stm32 common registers, compatible dependent data
	41	+ * struct stm32_adc_common_regs - stm32 common registers
26	42	* @csr: common status register offset
27		- * @eoc1: adc1 end of conversion flag in @csr
28		- * @eoc2: adc2 end of conversion flag in @csr
29		- * @eoc3: adc3 end of conversion flag in @csr
	43	+ * @ccr: common control register offset
	44	+ * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
	45	+ * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
30	46	* @ier: interrupt enable register offset for each adc
31	47	* @eocie_msk: end of conversion interrupt enable mask in @ier
32	48	*/
33	49	struct stm32_adc_common_regs {
34	50	u32 csr;
35		- u32 eoc1_msk;
36		- u32 eoc2_msk;
37		- u32 eoc3_msk;
	51	+ u32 ccr;
	52	+ u32 eoc_msk[STM32_ADC_MAX_ADCS];
	53	+ u32 ovr_msk[STM32_ADC_MAX_ADCS];
38	54	u32 ier;
39	55	u32 eocie_msk;
40	56	};
..	..	@@ -42,15 +58,21 @@
42	58	struct stm32_adc_priv;
43	59
44	60	/**
45		- * stm32_adc_priv_cfg - stm32 core compatible configuration data
	61	+ * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
46	62	* @regs: common registers for all instances
47	63	* @clk_sel: clock selection routine
48	64	* @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
	65	+ * @has_syscfg: SYSCFG capability flags
	66	+ * @num_irqs: number of interrupt lines
	67	+ * @num_adcs: maximum number of ADC instances in the common registers
49	68	*/
50	69	struct stm32_adc_priv_cfg {
51	70	const struct stm32_adc_common_regs *regs;
52	71	int (clk_sel)(struct platform_device , struct stm32_adc_priv *);
53	72	u32 max_clk_rate_hz;
	73	+ unsigned int has_syscfg;
	74	+ unsigned int num_irqs;
	75	+ unsigned int num_adcs;
54	76	};
55	77
56	78	/**
..	..	@@ -59,18 +81,34 @@
59	81	* @domain: irq domain reference
60	82	* @aclk: clock reference for the analog circuitry
61	83	* @bclk: bus clock common for all ADCs, depends on part used
	84	+ * @max_clk_rate: desired maximum clock rate
	85	+ * @booster: booster supply reference
	86	+ * @vdd: vdd supply reference
	87	+ * @vdda: vdda analog supply reference
62	88	* @vref: regulator reference
	89	+ * @vdd_uv: vdd supply voltage (microvolts)
	90	+ * @vdda_uv: vdda supply voltage (microvolts)
63	91	* @cfg: compatible configuration data
64	92	* @common: common data for all ADC instances
	93	+ * @ccr_bak: backup CCR in low power mode
	94	+ * @syscfg: reference to syscon, system control registers
65	95	*/
66	96	struct stm32_adc_priv {
67	97	int irq[STM32_ADC_MAX_ADCS];
68	98	struct irq_domain *domain;
69	99	struct clk *aclk;
70	100	struct clk *bclk;
	101	+ u32 max_clk_rate;
	102	+ struct regulator *booster;
	103	+ struct regulator *vdd;
	104	+ struct regulator *vdda;
71	105	struct regulator *vref;
	106	+ int vdd_uv;
	107	+ int vdda_uv;
72	108	const struct stm32_adc_priv_cfg *cfg;
73	109	struct stm32_adc_common common;
	110	+ u32 ccr_bak;
	111	+ struct regmap *syscfg;
74	112	};
75	113
76	114	static struct stm32_adc_priv to_stm32_adc_priv(struct stm32_adc_common com)
..	..	@@ -83,6 +121,7 @@
83	121
84	122	/**
85	123	* stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
	124	+ * @pdev: platform device
86	125	* @priv: stm32 ADC core private data
87	126	* Select clock prescaler used for analog conversions, before using ADC.
88	127	*/
..	..	@@ -106,7 +145,7 @@
106	145	}
107	146
108	147	for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
109		- if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
	148	+ if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
110	149	break;
111	150	}
112	151	if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
..	..	@@ -195,7 +234,7 @@
195	234	if (ckmode)
196	235	continue;
197	236
198		- if ((rate / div) <= priv->cfg->max_clk_rate_hz)
	237	+ if ((rate / div) <= priv->max_clk_rate)
199	238	goto out;
200	239	}
201	240	}
..	..	@@ -215,7 +254,7 @@
215	254	if (!ckmode)
216	255	continue;
217	256
218		- if ((rate / div) <= priv->cfg->max_clk_rate_hz)
	257	+ if ((rate / div) <= priv->max_clk_rate)
219	258	goto out;
220	259	}
221	260
..	..	@@ -242,9 +281,9 @@
242	281	/* STM32F4 common registers definitions */
243	282	static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
244	283	.csr = STM32F4_ADC_CSR,
245		- .eoc1_msk = STM32F4_EOC1,
246		- .eoc2_msk = STM32F4_EOC2,
247		- .eoc3_msk = STM32F4_EOC3,
	284	+ .ccr = STM32F4_ADC_CCR,
	285	+ .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
	286	+ .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
248	287	.ier = STM32F4_ADC_CR1,
249	288	.eocie_msk = STM32F4_EOCIE,
250	289	};
..	..	@@ -252,8 +291,9 @@
252	291	/* STM32H7 common registers definitions */
253	292	static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
254	293	.csr = STM32H7_ADC_CSR,
255		- .eoc1_msk = STM32H7_EOC_MST,
256		- .eoc2_msk = STM32H7_EOC_SLV,
	294	+ .ccr = STM32H7_ADC_CCR,
	295	+ .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
	296	+ .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
257	297	.ier = STM32H7_ADC_IER,
258	298	.eocie_msk = STM32H7_EOCIE,
259	299	};
..	..	@@ -277,6 +317,7 @@
277	317	{
278	318	struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
279	319	struct irq_chip *chip = irq_desc_get_chip(desc);
	320	+ int i;
280	321	u32 status;
281	322
282	323	chained_irq_enter(chip, desc);
..	..	@@ -294,17 +335,12 @@
294	335	* before invoking the interrupt handler (e.g. call ISR only for
295	336	* IRQ-enabled ADCs).
296	337	*/
297		- if (status & priv->cfg->regs->eoc1_msk &&
298		- stm32_adc_eoc_enabled(priv, 0))
299		- generic_handle_irq(irq_find_mapping(priv->domain, 0));
300		-
301		- if (status & priv->cfg->regs->eoc2_msk &&
302		- stm32_adc_eoc_enabled(priv, 1))
303		- generic_handle_irq(irq_find_mapping(priv->domain, 1));
304		-
305		- if (status & priv->cfg->regs->eoc3_msk &&
306		- stm32_adc_eoc_enabled(priv, 2))
307		- generic_handle_irq(irq_find_mapping(priv->domain, 2));
	338	+ for (i = 0; i < priv->cfg->num_adcs; i++) {
	339	+ if ((status & priv->cfg->regs->eoc_msk[i] &&
	340	+ stm32_adc_eoc_enabled(priv, i)) \|\|
	341	+ (status & priv->cfg->regs->ovr_msk[i]))
	342	+ generic_handle_irq(irq_find_mapping(priv->domain, i));
	343	+ }
308	344
309	345	chained_irq_exit(chip, desc);
310	346	};
..	..	@@ -336,22 +372,15 @@
336	372	struct device_node *np = pdev->dev.of_node;
337	373	unsigned int i;
338	374
339		- for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
	375	+ /*
	376	+ * Interrupt(s) must be provided, depending on the compatible:
	377	+ * - stm32f4/h7 shares a common interrupt line.
	378	+ * - stm32mp1, has one line per ADC
	379	+ */
	380	+ for (i = 0; i < priv->cfg->num_irqs; i++) {
340	381	priv->irq[i] = platform_get_irq(pdev, i);
341		- if (priv->irq[i] < 0) {
342		- /*
343		- * At least one interrupt must be provided, make others
344		- * optional:
345		- * - stm32f4/h7 shares a common interrupt.
346		- * - stm32mp1, has one line per ADC (either for ADC1,
347		- * ADC2 or both).
348		- */
349		- if (i && priv->irq[i] == -ENXIO)
350		- continue;
351		- dev_err(&pdev->dev, "failed to get irq\n");
352		-
	382	+ if (priv->irq[i] < 0)
353	383	return priv->irq[i];
354		- }
355	384	}
356	385
357	386	priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
..	..	@@ -362,9 +391,7 @@
362	391	return -ENOMEM;
363	392	}
364	393
365		- for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
366		- if (priv->irq[i] < 0)
367		- continue;
	394	+ for (i = 0; i < priv->cfg->num_irqs; i++) {
368	395	irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
369	396	irq_set_handler_data(priv->irq[i], priv);
370	397	}
..	..	@@ -382,11 +409,225 @@
382	409	irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
383	410	irq_domain_remove(priv->domain);
384	411
385		- for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
386		- if (priv->irq[i] < 0)
387		- continue;
	412	+ for (i = 0; i < priv->cfg->num_irqs; i++)
388	413	irq_set_chained_handler(priv->irq[i], NULL);
	414	+}
	415	+
	416	+static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
	417	+ struct device *dev)
	418	+{
	419	+ int ret;
	420	+
	421	+ /*
	422	+ * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
	423	+ * switches (via PCSEL) which have reduced performances when their
	424	+ * supply is below 2.7V (vdda by default):
	425	+ * - Voltage booster can be used, to get full ADC performances
	426	+ * (increases power consumption).
	427	+ * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
	428	+ *
	429	+ * Recommended settings for ANASWVDD and EN_BOOSTER:
	430	+ * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
	431	+ * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
	432	+ * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
	433	+ */
	434	+ if (priv->vdda_uv < 2700000) {
	435	+ if (priv->syscfg && priv->vdd_uv > 2700000) {
	436	+ ret = regulator_enable(priv->vdd);
	437	+ if (ret < 0) {
	438	+ dev_err(dev, "vdd enable failed %d\n", ret);
	439	+ return ret;
	440	+ }
	441	+
	442	+ ret = regmap_write(priv->syscfg,
	443	+ STM32MP1_SYSCFG_PMCSETR,
	444	+ STM32MP1_SYSCFG_ANASWVDD_MASK);
	445	+ if (ret < 0) {
	446	+ regulator_disable(priv->vdd);
	447	+ dev_err(dev, "vdd select failed, %d\n", ret);
	448	+ return ret;
	449	+ }
	450	+ dev_dbg(dev, "analog switches supplied by vdd\n");
	451	+
	452	+ return 0;
	453	+ }
	454	+
	455	+ if (priv->booster) {
	456	+ /*
	457	+ * This is optional, as this is a trade-off between
	458	+ * analog performance and power consumption.
	459	+ */
	460	+ ret = regulator_enable(priv->booster);
	461	+ if (ret < 0) {
	462	+ dev_err(dev, "booster enable failed %d\n", ret);
	463	+ return ret;
	464	+ }
	465	+ dev_dbg(dev, "analog switches supplied by booster\n");
	466	+
	467	+ return 0;
	468	+ }
389	469	}
	470	+
	471	+ /* Fallback using vdda (default), nothing to do */
	472	+ dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
	473	+ priv->vdda_uv);
	474	+
	475	+ return 0;
	476	+}
	477	+
	478	+static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
	479	+{
	480	+ if (priv->vdda_uv < 2700000) {
	481	+ if (priv->syscfg && priv->vdd_uv > 2700000) {
	482	+ regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
	483	+ STM32MP1_SYSCFG_ANASWVDD_MASK);
	484	+ regulator_disable(priv->vdd);
	485	+ return;
	486	+ }
	487	+ if (priv->booster)
	488	+ regulator_disable(priv->booster);
	489	+ }
	490	+}
	491	+
	492	+static int stm32_adc_core_hw_start(struct device *dev)
	493	+{
	494	+ struct stm32_adc_common *common = dev_get_drvdata(dev);
	495	+ struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
	496	+ int ret;
	497	+
	498	+ ret = regulator_enable(priv->vdda);
	499	+ if (ret < 0) {
	500	+ dev_err(dev, "vdda enable failed %d\n", ret);
	501	+ return ret;
	502	+ }
	503	+
	504	+ ret = regulator_get_voltage(priv->vdda);
	505	+ if (ret < 0) {
	506	+ dev_err(dev, "vdda get voltage failed, %d\n", ret);
	507	+ goto err_vdda_disable;
	508	+ }
	509	+ priv->vdda_uv = ret;
	510	+
	511	+ ret = stm32_adc_core_switches_supply_en(priv, dev);
	512	+ if (ret < 0)
	513	+ goto err_vdda_disable;
	514	+
	515	+ ret = regulator_enable(priv->vref);
	516	+ if (ret < 0) {
	517	+ dev_err(dev, "vref enable failed\n");
	518	+ goto err_switches_dis;
	519	+ }
	520	+
	521	+ if (priv->bclk) {
	522	+ ret = clk_prepare_enable(priv->bclk);
	523	+ if (ret < 0) {
	524	+ dev_err(dev, "bus clk enable failed\n");
	525	+ goto err_regulator_disable;
	526	+ }
	527	+ }
	528	+
	529	+ if (priv->aclk) {
	530	+ ret = clk_prepare_enable(priv->aclk);
	531	+ if (ret < 0) {
	532	+ dev_err(dev, "adc clk enable failed\n");
	533	+ goto err_bclk_disable;
	534	+ }
	535	+ }
	536	+
	537	+ writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
	538	+
	539	+ return 0;
	540	+
	541	+err_bclk_disable:
	542	+ if (priv->bclk)
	543	+ clk_disable_unprepare(priv->bclk);
	544	+err_regulator_disable:
	545	+ regulator_disable(priv->vref);
	546	+err_switches_dis:
	547	+ stm32_adc_core_switches_supply_dis(priv);
	548	+err_vdda_disable:
	549	+ regulator_disable(priv->vdda);
	550	+
	551	+ return ret;
	552	+}
	553	+
	554	+static void stm32_adc_core_hw_stop(struct device *dev)
	555	+{
	556	+ struct stm32_adc_common *common = dev_get_drvdata(dev);
	557	+ struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
	558	+
	559	+ /* Backup CCR that may be lost (depends on power state to achieve) */
	560	+ priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
	561	+ if (priv->aclk)
	562	+ clk_disable_unprepare(priv->aclk);
	563	+ if (priv->bclk)
	564	+ clk_disable_unprepare(priv->bclk);
	565	+ regulator_disable(priv->vref);
	566	+ stm32_adc_core_switches_supply_dis(priv);
	567	+ regulator_disable(priv->vdda);
	568	+}
	569	+
	570	+static int stm32_adc_core_switches_probe(struct device *dev,
	571	+ struct stm32_adc_priv *priv)
	572	+{
	573	+ struct device_node *np = dev->of_node;
	574	+ int ret;
	575	+
	576	+ /* Analog switches supply can be controlled by syscfg (optional) */
	577	+ priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
	578	+ if (IS_ERR(priv->syscfg)) {
	579	+ ret = PTR_ERR(priv->syscfg);
	580	+ if (ret != -ENODEV)
	581	+ return dev_err_probe(dev, ret, "Can't probe syscfg\n");
	582	+
	583	+ priv->syscfg = NULL;
	584	+ }
	585	+
	586	+ /* Booster can be used to supply analog switches (optional) */
	587	+ if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
	588	+ of_property_read_bool(np, "booster-supply")) {
	589	+ priv->booster = devm_regulator_get_optional(dev, "booster");
	590	+ if (IS_ERR(priv->booster)) {
	591	+ ret = PTR_ERR(priv->booster);
	592	+ if (ret != -ENODEV)
	593	+ return dev_err_probe(dev, ret, "can't get booster\n");
	594	+
	595	+ priv->booster = NULL;
	596	+ }
	597	+ }
	598	+
	599	+ /* Vdd can be used to supply analog switches (optional) */
	600	+ if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
	601	+ of_property_read_bool(np, "vdd-supply")) {
	602	+ priv->vdd = devm_regulator_get_optional(dev, "vdd");
	603	+ if (IS_ERR(priv->vdd)) {
	604	+ ret = PTR_ERR(priv->vdd);
	605	+ if (ret != -ENODEV)
	606	+ return dev_err_probe(dev, ret, "can't get vdd\n");
	607	+
	608	+ priv->vdd = NULL;
	609	+ }
	610	+ }
	611	+
	612	+ if (priv->vdd) {
	613	+ ret = regulator_enable(priv->vdd);
	614	+ if (ret < 0) {
	615	+ dev_err(dev, "vdd enable failed %d\n", ret);
	616	+ return ret;
	617	+ }
	618	+
	619	+ ret = regulator_get_voltage(priv->vdd);
	620	+ if (ret < 0) {
	621	+ dev_err(dev, "vdd get voltage failed %d\n", ret);
	622	+ regulator_disable(priv->vdd);
	623	+ return ret;
	624	+ }
	625	+ priv->vdd_uv = ret;
	626	+
	627	+ regulator_disable(priv->vdd);
	628	+ }
	629	+
	630	+ return 0;
390	631	}
391	632
392	633	static int stm32_adc_probe(struct platform_device *pdev)
..	..	@@ -395,6 +636,7 @@
395	636	struct device *dev = &pdev->dev;
396	637	struct device_node *np = pdev->dev.of_node;
397	638	struct resource *res;
	639	+ u32 max_rate;
398	640	int ret;
399	641
400	642	if (!pdev->dev.of_node)
..	..	@@ -403,6 +645,7 @@
403	645	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
404	646	if (!priv)
405	647	return -ENOMEM;
	648	+ platform_set_drvdata(pdev, &priv->common);
406	649
407	650	priv->cfg = (const struct stm32_adc_priv_cfg *)
408	651	of_match_device(dev->driver->of_match_table, dev)->data;
..	..	@@ -413,74 +656,62 @@
413	656	return PTR_ERR(priv->common.base);
414	657	priv->common.phys_base = res->start;
415	658
416		- priv->vref = devm_regulator_get(&pdev->dev, "vref");
417		- if (IS_ERR(priv->vref)) {
418		- ret = PTR_ERR(priv->vref);
419		- dev_err(&pdev->dev, "vref get failed, %d\n", ret);
420		- return ret;
421		- }
	659	+ priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
	660	+ if (IS_ERR(priv->vdda))
	661	+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
	662	+ "vdda get failed\n");
422	663
423		- ret = regulator_enable(priv->vref);
424		- if (ret < 0) {
425		- dev_err(&pdev->dev, "vref enable failed\n");
	664	+ priv->vref = devm_regulator_get(&pdev->dev, "vref");
	665	+ if (IS_ERR(priv->vref))
	666	+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
	667	+ "vref get failed\n");
	668	+
	669	+ priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
	670	+ if (IS_ERR(priv->aclk))
	671	+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
	672	+ "Can't get 'adc' clock\n");
	673	+
	674	+ priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
	675	+ if (IS_ERR(priv->bclk))
	676	+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
	677	+ "Can't get 'bus' clock\n");
	678	+
	679	+ ret = stm32_adc_core_switches_probe(dev, priv);
	680	+ if (ret)
426	681	return ret;
427		- }
	682	+
	683	+ pm_runtime_get_noresume(dev);
	684	+ pm_runtime_set_active(dev);
	685	+ pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
	686	+ pm_runtime_use_autosuspend(dev);
	687	+ pm_runtime_enable(dev);
	688	+
	689	+ ret = stm32_adc_core_hw_start(dev);
	690	+ if (ret)
	691	+ goto err_pm_stop;
428	692
429	693	ret = regulator_get_voltage(priv->vref);
430	694	if (ret < 0) {
431	695	dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
432		- goto err_regulator_disable;
	696	+ goto err_hw_stop;
433	697	}
434	698	priv->common.vref_mv = ret / 1000;
435	699	dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
436	700
437		- priv->aclk = devm_clk_get(&pdev->dev, "adc");
438		- if (IS_ERR(priv->aclk)) {
439		- ret = PTR_ERR(priv->aclk);
440		- if (ret == -ENOENT) {
441		- priv->aclk = NULL;
442		- } else {
443		- dev_err(&pdev->dev, "Can't get 'adc' clock\n");
444		- goto err_regulator_disable;
445		- }
446		- }
447		-
448		- if (priv->aclk) {
449		- ret = clk_prepare_enable(priv->aclk);
450		- if (ret < 0) {
451		- dev_err(&pdev->dev, "adc clk enable failed\n");
452		- goto err_regulator_disable;
453		- }
454		- }
455		-
456		- priv->bclk = devm_clk_get(&pdev->dev, "bus");
457		- if (IS_ERR(priv->bclk)) {
458		- ret = PTR_ERR(priv->bclk);
459		- if (ret == -ENOENT) {
460		- priv->bclk = NULL;
461		- } else {
462		- dev_err(&pdev->dev, "Can't get 'bus' clock\n");
463		- goto err_aclk_disable;
464		- }
465		- }
466		-
467		- if (priv->bclk) {
468		- ret = clk_prepare_enable(priv->bclk);
469		- if (ret < 0) {
470		- dev_err(&pdev->dev, "adc clk enable failed\n");
471		- goto err_aclk_disable;
472		- }
473		- }
	701	+ ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
	702	+ &max_rate);
	703	+ if (!ret)
	704	+ priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
	705	+ else
	706	+ priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
474	707
475	708	ret = priv->cfg->clk_sel(pdev, priv);
476	709	if (ret < 0)
477		- goto err_bclk_disable;
	710	+ goto err_hw_stop;
478	711
479	712	ret = stm32_adc_irq_probe(pdev, priv);
480	713	if (ret < 0)
481		- goto err_bclk_disable;
482		-
483		- platform_set_drvdata(pdev, &priv->common);
	714	+ goto err_hw_stop;
484	715
485	716	ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
486	717	if (ret < 0) {
..	..	@@ -488,21 +719,19 @@
488	719	goto err_irq_remove;
489	720	}
490	721
	722	+ pm_runtime_mark_last_busy(dev);
	723	+ pm_runtime_put_autosuspend(dev);
	724	+
491	725	return 0;
492	726
493	727	err_irq_remove:
494	728	stm32_adc_irq_remove(pdev, priv);
495		-
496		-err_bclk_disable:
497		- if (priv->bclk)
498		- clk_disable_unprepare(priv->bclk);
499		-
500		-err_aclk_disable:
501		- if (priv->aclk)
502		- clk_disable_unprepare(priv->aclk);
503		-
504		-err_regulator_disable:
505		- regulator_disable(priv->vref);
	729	+err_hw_stop:
	730	+ stm32_adc_core_hw_stop(dev);
	731	+err_pm_stop:
	732	+ pm_runtime_disable(dev);
	733	+ pm_runtime_set_suspended(dev);
	734	+ pm_runtime_put_noidle(dev);
506	735
507	736	return ret;
508	737	}
..	..	@@ -512,33 +741,70 @@
512	741	struct stm32_adc_common *common = platform_get_drvdata(pdev);
513	742	struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
514	743
	744	+ pm_runtime_get_sync(&pdev->dev);
515	745	of_platform_depopulate(&pdev->dev);
516	746	stm32_adc_irq_remove(pdev, priv);
517		- if (priv->bclk)
518		- clk_disable_unprepare(priv->bclk);
519		- if (priv->aclk)
520		- clk_disable_unprepare(priv->aclk);
521		- regulator_disable(priv->vref);
	747	+ stm32_adc_core_hw_stop(&pdev->dev);
	748	+ pm_runtime_disable(&pdev->dev);
	749	+ pm_runtime_set_suspended(&pdev->dev);
	750	+ pm_runtime_put_noidle(&pdev->dev);
522	751
523	752	return 0;
524	753	}
	754	+
	755	+#if defined(CONFIG_PM)
	756	+static int stm32_adc_core_runtime_suspend(struct device *dev)
	757	+{
	758	+ stm32_adc_core_hw_stop(dev);
	759	+
	760	+ return 0;
	761	+}
	762	+
	763	+static int stm32_adc_core_runtime_resume(struct device *dev)
	764	+{
	765	+ return stm32_adc_core_hw_start(dev);
	766	+}
	767	+
	768	+static int stm32_adc_core_runtime_idle(struct device *dev)
	769	+{
	770	+ pm_runtime_mark_last_busy(dev);
	771	+
	772	+ return 0;
	773	+}
	774	+#endif
	775	+
	776	+static const struct dev_pm_ops stm32_adc_core_pm_ops = {
	777	+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	778	+ pm_runtime_force_resume)
	779	+ SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
	780	+ stm32_adc_core_runtime_resume,
	781	+ stm32_adc_core_runtime_idle)
	782	+};
525	783
526	784	static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
527	785	.regs = &stm32f4_adc_common_regs,
528	786	.clk_sel = stm32f4_adc_clk_sel,
529	787	.max_clk_rate_hz = 36000000,
	788	+ .num_irqs = 1,
	789	+ .num_adcs = 3,
530	790	};
531	791
532	792	static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
533	793	.regs = &stm32h7_adc_common_regs,
534	794	.clk_sel = stm32h7_adc_clk_sel,
535	795	.max_clk_rate_hz = 36000000,
	796	+ .has_syscfg = HAS_VBOOSTER,
	797	+ .num_irqs = 1,
	798	+ .num_adcs = 2,
536	799	};
537	800
538	801	static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
539	802	.regs = &stm32h7_adc_common_regs,
540	803	.clk_sel = stm32h7_adc_clk_sel,
541		- .max_clk_rate_hz = 40000000,
	804	+ .max_clk_rate_hz = 36000000,
	805	+ .has_syscfg = HAS_VBOOSTER \| HAS_ANASWVDD,
	806	+ .num_irqs = 2,
	807	+ .num_adcs = 2,
542	808	};
543	809
544	810	static const struct of_device_id stm32_adc_of_match[] = {
..	..	@@ -562,6 +828,7 @@
562	828	.driver = {
563	829	.name = "stm32-adc-core",
564	830	.of_match_table = stm32_adc_of_match,
	831	+ .pm = &stm32_adc_core_pm_ops,
565	832	},
566	833	};
567	834	module_platform_driver(stm32_adc_driver);