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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/i2c/busses/i2c-xiic.c
....@@ -1,17 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * i2c-xiic.c
34  * Copyright (c) 2002-2007 Xilinx Inc.
45  * Copyright (c) 2009-2010 Intel Corporation
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
14
- *
156  *
167  * This code was implemented by Mocean Laboratories AB when porting linux
178  * to the automotive development board Russellville. The copyright holder
....@@ -55,32 +46,36 @@
5546 
5647 /**
5748  * struct xiic_i2c - Internal representation of the XIIC I2C bus
58
- * @base:	Memory base of the HW registers
59
- * @wait:	Wait queue for callers
60
- * @adap:	Kernel adapter representation
61
- * @tx_msg:	Messages from above to be sent
62
- * @lock:	Mutual exclusion
63
- * @tx_pos:	Current pos in TX message
64
- * @nmsgs:	Number of messages in tx_msg
65
- * @state:	See STATE_
66
- * @rx_msg:	Current RX message
67
- * @rx_pos:	Position within current RX message
49
+ * @dev: Pointer to device structure
50
+ * @base: Memory base of the HW registers
51
+ * @wait: Wait queue for callers
52
+ * @adap: Kernel adapter representation
53
+ * @tx_msg: Messages from above to be sent
54
+ * @lock: Mutual exclusion
55
+ * @tx_pos: Current pos in TX message
56
+ * @nmsgs: Number of messages in tx_msg
57
+ * @rx_msg: Current RX message
58
+ * @rx_pos: Position within current RX message
6859  * @endianness: big/little-endian byte order
60
+ * @clk: Pointer to AXI4-lite input clock
61
+ * @state: See STATE_
62
+ * @singlemaster: Indicates bus is single master
6963  */
7064 struct xiic_i2c {
71
-	struct device		*dev;
72
-	void __iomem		*base;
73
-	wait_queue_head_t	wait;
74
-	struct i2c_adapter	adap;
75
-	struct i2c_msg		*tx_msg;
76
-	struct mutex		lock;
77
-	unsigned int		tx_pos;
78
-	unsigned int		nmsgs;
79
-	enum xilinx_i2c_state	state;
80
-	struct i2c_msg		*rx_msg;
81
-	int			rx_pos;
82
-	enum xiic_endian	endianness;
65
+	struct device *dev;
66
+	void __iomem *base;
67
+	wait_queue_head_t wait;
68
+	struct i2c_adapter adap;
69
+	struct i2c_msg *tx_msg;
70
+	struct mutex lock;
71
+	unsigned int tx_pos;
72
+	unsigned int nmsgs;
73
+	struct i2c_msg *rx_msg;
74
+	int rx_pos;
75
+	enum xiic_endian endianness;
8376 	struct clk *clk;
77
+	enum xilinx_i2c_state state;
78
+	bool singlemaster;
8479 };
8580 
8681 
....@@ -163,6 +158,8 @@
163158 #define XIIC_RESET_MASK             0xAUL
164159 
165160 #define XIIC_PM_TIMEOUT		1000	/* ms */
161
+/* timeout waiting for the controller to respond */
162
+#define XIIC_I2C_TIMEOUT	(msecs_to_jiffies(1000))
166163 /*
167164  * The following constant is used for the device global interrupt enable
168165  * register, to enable all interrupts for the device, this is the only bit
....@@ -173,7 +170,7 @@
173170 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
174171 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
175172 
176
-static void xiic_start_xfer(struct xiic_i2c *i2c);
173
+static int xiic_start_xfer(struct xiic_i2c *i2c);
177174 static void __xiic_start_xfer(struct xiic_i2c *i2c);
178175 
179176 /*
....@@ -254,17 +251,29 @@
254251 	xiic_irq_en(i2c, mask);
255252 }
256253 
257
-static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
254
+static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
258255 {
259256 	u8 sr;
257
+	unsigned long timeout;
258
+
259
+	timeout = jiffies + XIIC_I2C_TIMEOUT;
260260 	for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
261261 		!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
262
-		sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
262
+		sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
263263 		xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
264
+		if (time_after(jiffies, timeout)) {
265
+			dev_err(i2c->dev, "Failed to clear rx fifo\n");
266
+			return -ETIMEDOUT;
267
+		}
268
+	}
269
+
270
+	return 0;
264271 }
265272 
266
-static void xiic_reinit(struct xiic_i2c *i2c)
273
+static int xiic_reinit(struct xiic_i2c *i2c)
267274 {
275
+	int ret;
276
+
268277 	xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
269278 
270279 	/* Set receive Fifo depth to maximum (zero based). */
....@@ -277,12 +286,16 @@
277286 	xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
278287 
279288 	/* make sure RX fifo is empty */
280
-	xiic_clear_rx_fifo(i2c);
289
+	ret = xiic_clear_rx_fifo(i2c);
290
+	if (ret)
291
+		return ret;
281292 
282293 	/* Enable interrupts */
283294 	xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
284295 
285296 	xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
297
+
298
+	return 0;
286299 }
287300 
288301 static void xiic_deinit(struct xiic_i2c *i2c)
....@@ -362,6 +375,9 @@
362375 	struct xiic_i2c *i2c = dev_id;
363376 	u32 pend, isr, ier;
364377 	u32 clr = 0;
378
+	int xfer_more = 0;
379
+	int wakeup_req = 0;
380
+	int wakeup_code = 0;
365381 
366382 	/* Get the interrupt Status from the IPIF. There is no clearing of
367383 	 * interrupts in the IPIF. Interrupts must be cleared at the source.
....@@ -398,10 +414,16 @@
398414 		 */
399415 		xiic_reinit(i2c);
400416 
401
-		if (i2c->rx_msg)
402
-			xiic_wakeup(i2c, STATE_ERROR);
403
-		if (i2c->tx_msg)
404
-			xiic_wakeup(i2c, STATE_ERROR);
417
+		if (i2c->rx_msg) {
418
+			wakeup_req = 1;
419
+			wakeup_code = STATE_ERROR;
420
+		}
421
+		if (i2c->tx_msg) {
422
+			wakeup_req = 1;
423
+			wakeup_code = STATE_ERROR;
424
+		}
425
+		/* don't try to handle other events */
426
+		goto out;
405427 	}
406428 	if (pend & XIIC_INTR_RX_FULL_MASK) {
407429 		/* Receive register/FIFO is full */
....@@ -435,8 +457,7 @@
435457 				i2c->tx_msg++;
436458 				dev_dbg(i2c->adap.dev.parent,
437459 					"%s will start next...\n", __func__);
438
-
439
-				__xiic_start_xfer(i2c);
460
+				xfer_more = 1;
440461 			}
441462 		}
442463 	}
....@@ -450,11 +471,13 @@
450471 		if (!i2c->tx_msg)
451472 			goto out;
452473 
453
-		if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
454
-			xiic_tx_space(i2c) == 0)
455
-			xiic_wakeup(i2c, STATE_DONE);
474
+		wakeup_req = 1;
475
+
476
+		if (i2c->nmsgs == 1 && !i2c->rx_msg &&
477
+		    xiic_tx_space(i2c) == 0)
478
+			wakeup_code = STATE_DONE;
456479 		else
457
-			xiic_wakeup(i2c, STATE_ERROR);
480
+			wakeup_code = STATE_ERROR;
458481 	}
459482 	if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
460483 		/* Transmit register/FIFO is empty or ½ empty */
....@@ -478,7 +501,7 @@
478501 			if (i2c->nmsgs > 1) {
479502 				i2c->nmsgs--;
480503 				i2c->tx_msg++;
481
-				__xiic_start_xfer(i2c);
504
+				xfer_more = 1;
482505 			} else {
483506 				xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
484507 
....@@ -496,6 +519,13 @@
496519 	dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
497520 
498521 	xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
522
+	if (xfer_more)
523
+		__xiic_start_xfer(i2c);
524
+	if (wakeup_req)
525
+		xiic_wakeup(i2c, wakeup_code);
526
+
527
+	WARN_ON(xfer_more && wakeup_req);
528
+
499529 	mutex_unlock(&i2c->lock);
500530 	return IRQ_HANDLED;
501531 }
....@@ -514,6 +544,15 @@
514544 
515545 	if (i2c->tx_msg)
516546 		return -EBUSY;
547
+
548
+	/* In single master mode bus can only be busy, when in use by this
549
+	 * driver. If the register indicates bus being busy for some reason we
550
+	 * should ignore it, since bus will never be released and i2c will be
551
+	 * stuck forever.
552
+	 */
553
+	if (i2c->singlemaster) {
554
+		return 0;
555
+	}
517556 
518557 	/* for instance if previous transfer was terminated due to TX error
519558 	 * it might be that the bus is on it's way to become available
....@@ -662,12 +701,18 @@
662701 
663702 }
664703 
665
-static void xiic_start_xfer(struct xiic_i2c *i2c)
704
+static int xiic_start_xfer(struct xiic_i2c *i2c)
666705 {
706
+	int ret;
667707 	mutex_lock(&i2c->lock);
668
-	xiic_reinit(i2c);
669
-	__xiic_start_xfer(i2c);
708
+
709
+	ret = xiic_reinit(i2c);
710
+	if (!ret)
711
+		__xiic_start_xfer(i2c);
712
+
670713 	mutex_unlock(&i2c->lock);
714
+
715
+	return ret;
671716 }
672717 
673718 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
....@@ -678,7 +723,7 @@
678723 	dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
679724 		xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
680725 
681
-	err = pm_runtime_get_sync(i2c->dev);
726
+	err = pm_runtime_resume_and_get(i2c->dev);
682727 	if (err < 0)
683728 		return err;
684729 
....@@ -689,7 +734,11 @@
689734 	i2c->tx_msg = msgs;
690735 	i2c->nmsgs = num;
691736 
692
-	xiic_start_xfer(i2c);
737
+	err = xiic_start_xfer(i2c);
738
+	if (err < 0) {
739
+		dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
740
+		goto out;
741
+	}
693742 
694743 	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
695744 		(i2c->state == STATE_DONE), HZ)) {
....@@ -724,7 +773,6 @@
724773 
725774 static const struct i2c_adapter xiic_adapter = {
726775 	.owner = THIS_MODULE,
727
-	.name = DRIVER_NAME,
728776 	.class = I2C_CLASS_DEPRECATED,
729777 	.algo = &xiic_algorithm,
730778 	.quirks = &xiic_quirks,
....@@ -761,13 +809,16 @@
761809 	i2c_set_adapdata(&i2c->adap, i2c);
762810 	i2c->adap.dev.parent = &pdev->dev;
763811 	i2c->adap.dev.of_node = pdev->dev.of_node;
812
+	snprintf(i2c->adap.name, sizeof(i2c->adap.name),
813
+		 DRIVER_NAME " %s", pdev->name);
764814 
765815 	mutex_init(&i2c->lock);
766816 	init_waitqueue_head(&i2c->wait);
767817 
768818 	i2c->clk = devm_clk_get(&pdev->dev, NULL);
769819 	if (IS_ERR(i2c->clk)) {
770
-		dev_err(&pdev->dev, "input clock not found.\n");
820
+		if (PTR_ERR(i2c->clk) != -EPROBE_DEFER)
821
+			dev_err(&pdev->dev, "input clock not found.\n");
771822 		return PTR_ERR(i2c->clk);
772823 	}
773824 	ret = clk_prepare_enable(i2c->clk);
....@@ -776,10 +827,10 @@
776827 		return ret;
777828 	}
778829 	i2c->dev = &pdev->dev;
779
-	pm_runtime_enable(i2c->dev);
780830 	pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
781831 	pm_runtime_use_autosuspend(i2c->dev);
782832 	pm_runtime_set_active(i2c->dev);
833
+	pm_runtime_enable(i2c->dev);
783834 	ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
784835 					xiic_process, IRQF_ONESHOT,
785836 					pdev->name, i2c);
....@@ -788,6 +839,9 @@
788839 		dev_err(&pdev->dev, "Cannot claim IRQ\n");
789840 		goto err_clk_dis;
790841 	}
842
+
843
+	i2c->singlemaster =
844
+		of_property_read_bool(pdev->dev.of_node, "single-master");
791845 
792846 	/*
793847 	 * Detect endianness
....@@ -801,7 +855,11 @@
801855 	if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
802856 		i2c->endianness = BIG;
803857 
804
-	xiic_reinit(i2c);
858
+	ret = xiic_reinit(i2c);
859
+	if (ret < 0) {
860
+		dev_err(&pdev->dev, "Cannot xiic_reinit\n");
861
+		goto err_clk_dis;
862
+	}
805863 
806864 	/* add i2c adapter to i2c tree */
807865 	ret = i2c_add_adapter(&i2c->adap);
....@@ -813,7 +871,7 @@
813871 	if (pdata) {
814872 		/* add in known devices to the bus */
815873 		for (i = 0; i < pdata->num_devices; i++)
816
-			i2c_new_device(&i2c->adap, pdata->devices + i);
874
+			i2c_new_client_device(&i2c->adap, pdata->devices + i);
817875 	}
818876 
819877 	return 0;
....@@ -833,14 +891,16 @@
833891 	/* remove adapter & data */
834892 	i2c_del_adapter(&i2c->adap);
835893 
836
-	ret = clk_prepare_enable(i2c->clk);
837
-	if (ret) {
838
-		dev_err(&pdev->dev, "Unable to enable clock.\n");
894
+	ret = pm_runtime_resume_and_get(i2c->dev);
895
+	if (ret < 0)
839896 		return ret;
840
-	}
897
+
841898 	xiic_deinit(i2c);
899
+	pm_runtime_put_sync(i2c->dev);
842900 	clk_disable_unprepare(i2c->clk);
843901 	pm_runtime_disable(&pdev->dev);
902
+	pm_runtime_set_suspended(&pdev->dev);
903
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
844904 
845905 	return 0;
846906 }
....@@ -892,6 +952,7 @@
892952 
893953 module_platform_driver(xiic_i2c_driver);
894954 
955
+MODULE_ALIAS("platform:" DRIVER_NAME);
895956 MODULE_AUTHOR("info@mocean-labs.com");
896957 MODULE_DESCRIPTION("Xilinx I2C bus driver");
897958 MODULE_LICENSE("GPL v2");