change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/gpu/drm/nouveau/nv50_fence.c
..
..
@@ -37,7 +37,7 @@
37
37
 {
38
38
 	struct nv10_fence_priv *priv = chan->drm->fence;
39
39
 	struct nv10_fence_chan *fctx;
40
-	struct ttm_mem_reg *reg = &priv->bo->bo.mem;
40
+	struct ttm_resource *reg = &priv->bo->bo.mem;
41
41
 	u32 start = reg->start * PAGE_SIZE;
42
42
 	u32 limit = start + reg->size - 1;
43
43
 	int ret;
..
..
@@ -51,7 +51,8 @@
51
51
 	fctx->base.read = nv10_fence_read;
52
52
 	fctx->base.sync = nv17_fence_sync;
53
53
 
54
-	ret = nvif_object_init(&chan->user, NvSema, NV_DMA_IN_MEMORY,
54
+	ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
55
+			       NV_DMA_IN_MEMORY,
55
56
 			       &(struct nv_dma_v0) {
56
57
 					.target = NV_DMA_V0_TARGET_VRAM,
57
58
 					.access = NV_DMA_V0_ACCESS_RDWR,
..
..
@@ -80,10 +81,11 @@
80
81
 	priv->base.context_del = nv10_fence_context_del;
81
82
 	spin_lock_init(&priv->lock);
82
83
 
83
-	ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
84
+	ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
85
+			     NOUVEAU_GEM_DOMAIN_VRAM,
84
86
 			     0, 0x0000, NULL, NULL, &priv->bo);
85
87
 	if (!ret) {
86
-		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
88
+		ret = nouveau_bo_pin(priv->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
87
89
 		if (!ret) {
88
90
 			ret = nouveau_bo_map(priv->bo);
89
91
 			if (ret)