~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,22 +1,8 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2015 MediaTek Inc.
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 as
6		- * published by the Free Software Foundation.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14		-#include <drm/drmP.h>
15		-#include <drm/drm_atomic_helper.h>
16		-#include <drm/drm_crtc_helper.h>
17		-#include <drm/drm_mipi_dsi.h>
18		-#include <drm/drm_panel.h>
19		-#include <drm/drm_of.h>
20	6	#include <linux/clk.h>
21	7	#include <linux/component.h>
22	8	#include <linux/iopoll.h>
..	..	@@ -25,8 +11,19 @@
25	11	#include <linux/of_platform.h>
26	12	#include <linux/phy/phy.h>
27	13	#include <linux/platform_device.h>
	14	+
28	15	#include <video/mipi_display.h>
29	16	#include <video/videomode.h>
	17	+
	18	+#include <drm/drm_atomic_helper.h>
	19	+#include <drm/drm_bridge.h>
	20	+#include <drm/drm_bridge_connector.h>
	21	+#include <drm/drm_mipi_dsi.h>
	22	+#include <drm/drm_of.h>
	23	+#include <drm/drm_panel.h>
	24	+#include <drm/drm_print.h>
	25	+#include <drm/drm_probe_helper.h>
	26	+#include <drm/drm_simple_kms_helper.h>
30	27
31	28	#include "mtk_drm_ddp_comp.h"
32	29
..	..	@@ -45,6 +42,7 @@
45	42	#define DSI_CON_CTRL 0x10
46	43	#define DSI_RESET BIT(0)
47	44	#define DSI_EN BIT(1)
	45	+#define DPHY_RESET BIT(2)
48	46
49	47	#define DSI_MODE_CTRL 0x14
50	48	#define MODE (3)
..	..	@@ -78,6 +76,7 @@
78	76	#define DSI_VBP_NL 0x24
79	77	#define DSI_VFP_NL 0x28
80	78	#define DSI_VACT_NL 0x2C
	79	+#define DSI_SIZE_CON 0x38
81	80	#define DSI_HSA_WC 0x50
82	81	#define DSI_HBP_WC 0x54
83	82	#define DSI_HFP_WC 0x58
..	..	@@ -131,7 +130,10 @@
131	130	#define VM_CMD_EN BIT(0)
132	131	#define TS_VFP_EN BIT(5)
133	132
134		-#define DSI_CMDQ0 0x180
	133	+#define DSI_SHADOW_DEBUG 0x190U
	134	+#define FORCE_COMMIT BIT(0)
	135	+#define BYPASS_SHADOW BIT(1)
	136	+
135	137	#define CONFIG (0xff << 0)
136	138	#define SHORT_PACKET 0
137	139	#define LONG_PACKET 2
..	..	@@ -139,12 +141,6 @@
139	141	#define DATA_ID (0xff << 8)
140	142	#define DATA_0 (0xff << 16)
141	143	#define DATA_1 (0xff << 24)
142		-
143		-#define T_LPX 5
144		-#define T_HS_PREP 6
145		-#define T_HS_TRAIL 8
146		-#define T_HS_EXIT 7
147		-#define T_HS_ZERO 10
148	144
149	145	#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
150	146
..	..	@@ -154,16 +150,41 @@
154	150	(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) \|\| \
155	151	(type == MIPI_DSI_DCS_READ))
156	152
	153	+struct mtk_phy_timing {
	154	+ u32 lpx;
	155	+ u32 da_hs_prepare;
	156	+ u32 da_hs_zero;
	157	+ u32 da_hs_trail;
	158	+
	159	+ u32 ta_go;
	160	+ u32 ta_sure;
	161	+ u32 ta_get;
	162	+ u32 da_hs_exit;
	163	+
	164	+ u32 clk_hs_zero;
	165	+ u32 clk_hs_trail;
	166	+
	167	+ u32 clk_hs_prepare;
	168	+ u32 clk_hs_post;
	169	+ u32 clk_hs_exit;
	170	+};
	171	+
157	172	struct phy;
	173	+
	174	+struct mtk_dsi_driver_data {
	175	+ const u32 reg_cmdq_off;
	176	+ bool has_shadow_ctl;
	177	+ bool has_size_ctl;
	178	+};
158	179
159	180	struct mtk_dsi {
160	181	struct mtk_ddp_comp ddp_comp;
161	182	struct device *dev;
162	183	struct mipi_dsi_host host;
163	184	struct drm_encoder encoder;
164		- struct drm_connector conn;
165		- struct drm_panel *panel;
166		- struct drm_bridge *bridge;
	185	+ struct drm_bridge bridge;
	186	+ struct drm_bridge *next_bridge;
	187	+ struct drm_connector *connector;
167	188	struct phy *phy;
168	189
169	190	void __iomem *regs;
..	..	@@ -178,20 +199,18 @@
178	199	enum mipi_dsi_pixel_format format;
179	200	unsigned int lanes;
180	201	struct videomode vm;
	202	+ struct mtk_phy_timing phy_timing;
181	203	int refcount;
182	204	bool enabled;
	205	+ bool lanes_ready;
183	206	u32 irq_data;
184	207	wait_queue_head_t irq_wait_queue;
	208	+ const struct mtk_dsi_driver_data *driver_data;
185	209	};
186	210
187		-static inline struct mtk_dsi encoder_to_dsi(struct drm_encoder e)
	211	+static inline struct mtk_dsi bridge_to_dsi(struct drm_bridge b)
188	212	{
189		- return container_of(e, struct mtk_dsi, encoder);
190		-}
191		-
192		-static inline struct mtk_dsi connector_to_dsi(struct drm_connector c)
193		-{
194		- return container_of(c, struct mtk_dsi, conn);
	213	+ return container_of(b, struct mtk_dsi, bridge);
195	214	}
196	215
197	216	static inline struct mtk_dsi host_to_dsi(struct mipi_dsi_host h)
..	..	@@ -209,18 +228,34 @@
209	228	static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
210	229	{
211	230	u32 timcon0, timcon1, timcon2, timcon3;
212		- u32 ui, cycle_time;
	231	+ u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
	232	+ struct mtk_phy_timing *timing = &dsi->phy_timing;
213	233
214		- ui = 1000 / dsi->data_rate + 0x01;
215		- cycle_time = 8000 / dsi->data_rate + 0x01;
	234	+ timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
	235	+ timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
	236	+ timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
	237	+ timing->da_hs_prepare;
	238	+ timing->da_hs_trail = timing->da_hs_prepare + 1;
216	239
217		- timcon0 = T_LPX \| T_HS_PREP << 8 \| T_HS_ZERO << 16 \| T_HS_TRAIL << 24;
218		- timcon1 = 4 * T_LPX \| (3 * T_LPX / 2) << 8 \| 5 * T_LPX << 16 \|
219		- T_HS_EXIT << 24;
220		- timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) \|
221		- (NS_TO_CYCLE(0x150, cycle_time) << 16);
222		- timcon3 = NS_TO_CYCLE(0x40, cycle_time) \| (2 * T_LPX) << 16 \|
223		- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
	240	+ timing->ta_go = 4 * timing->lpx - 2;
	241	+ timing->ta_sure = timing->lpx + 2;
	242	+ timing->ta_get = 4 * timing->lpx;
	243	+ timing->da_hs_exit = 2 * timing->lpx + 1;
	244	+
	245	+ timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
	246	+ timing->clk_hs_post = timing->clk_hs_prepare + 8;
	247	+ timing->clk_hs_trail = timing->clk_hs_prepare;
	248	+ timing->clk_hs_zero = timing->clk_hs_trail * 4;
	249	+ timing->clk_hs_exit = 2 * timing->clk_hs_trail;
	250	+
	251	+ timcon0 = timing->lpx \| timing->da_hs_prepare << 8 \|
	252	+ timing->da_hs_zero << 16 \| timing->da_hs_trail << 24;
	253	+ timcon1 = timing->ta_go \| timing->ta_sure << 8 \|
	254	+ timing->ta_get << 16 \| timing->da_hs_exit << 24;
	255	+ timcon2 = 1 << 8 \| timing->clk_hs_zero << 16 \|
	256	+ timing->clk_hs_trail << 24;
	257	+ timcon3 = timing->clk_hs_prepare \| timing->clk_hs_post << 8 \|
	258	+ timing->clk_hs_exit << 16;
224	259
225	260	writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
226	261	writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
..	..	@@ -242,6 +277,12 @@
242	277	{
243	278	mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
244	279	mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
	280	+}
	281	+
	282	+static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
	283	+{
	284	+ mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
	285	+ mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
245	286	}
246	287
247	288	static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
..	..	@@ -272,10 +313,7 @@
272	313
273	314	static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
274	315	{
275		- u32 tmp_reg1;
276		-
277		- tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
278		- return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
	316	+ return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
279	317	}
280	318
281	319	static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
..	..	@@ -407,7 +445,11 @@
407	445	u32 horizontal_sync_active_byte;
408	446	u32 horizontal_backporch_byte;
409	447	u32 horizontal_frontporch_byte;
410		- u32 dsi_tmp_buf_bpp;
	448	+ u32 horizontal_front_back_byte;
	449	+ u32 data_phy_cycles_byte;
	450	+ u32 dsi_tmp_buf_bpp, data_phy_cycles;
	451	+ u32 delta;
	452	+ struct mtk_phy_timing *timing = &dsi->phy_timing;
411	453
412	454	struct videomode *vm = &dsi->vm;
413	455
..	..	@@ -421,16 +463,38 @@
421	463	writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
422	464	writel(vm->vactive, dsi->regs + DSI_VACT_NL);
423	465
	466	+ if (dsi->driver_data->has_size_ctl)
	467	+ writel(vm->vactive << 16 \| vm->hactive,
	468	+ dsi->regs + DSI_SIZE_CON);
	469	+
424	470	horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
425	471
426	472	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
427		- horizontal_backporch_byte =
428		- (vm->hback_porch * dsi_tmp_buf_bpp - 10);
	473	+ horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;
429	474	else
430		- horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
431		- dsi_tmp_buf_bpp - 10);
	475	+ horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
	476	+ dsi_tmp_buf_bpp - 10;
432	477
433		- horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
	478	+ data_phy_cycles = timing->lpx + timing->da_hs_prepare +
	479	+ timing->da_hs_zero + timing->da_hs_exit + 3;
	480	+
	481	+ delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
	482	+
	483	+ horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;
	484	+ horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;
	485	+ data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
	486	+
	487	+ if (horizontal_front_back_byte > data_phy_cycles_byte) {
	488	+ horizontal_frontporch_byte -= data_phy_cycles_byte *
	489	+ horizontal_frontporch_byte /
	490	+ horizontal_front_back_byte;
	491	+
	492	+ horizontal_backporch_byte -= data_phy_cycles_byte *
	493	+ horizontal_backporch_byte /
	494	+ horizontal_front_back_byte;
	495	+ } else {
	496	+ DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
	497	+ }
434	498
435	499	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
436	500	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
..	..	@@ -528,10 +592,9 @@
528	592
529	593	static int mtk_dsi_poweron(struct mtk_dsi *dsi)
530	594	{
531		- struct device *dev = dsi->dev;
	595	+ struct device *dev = dsi->host.dev;
532	596	int ret;
533		- u64 pixel_clock, total_bits;
534		- u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
	597	+ u32 bit_per_pixel;
535	598
536	599	if (++dsi->refcount != 1)
537	600	return 0;
..	..	@@ -550,24 +613,8 @@
550	613	break;
551	614	}
552	615
553		- /**
554		- * htotal_time = htotal * byte_per_pixel / num_lanes
555		- * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
556		- * mipi_ratio = (htotal_time + overhead_time) / htotal_time
557		- * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
558		- */
559		- pixel_clock = dsi->vm.pixelclock;
560		- htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
561		- dsi->vm.hsync_len;
562		- htotal_bits = htotal * bit_per_pixel;
563		-
564		- overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
565		- T_HS_EXIT;
566		- overhead_bits = overhead_cycles * dsi->lanes * 8;
567		- total_bits = htotal_bits + overhead_bits;
568		-
569		- dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
570		- htotal * dsi->lanes);
	616	+ dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
	617	+ dsi->lanes);
571	618
572	619	ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
573	620	if (ret < 0) {
..	..	@@ -590,29 +637,20 @@
590	637	}
591	638
592	639	mtk_dsi_enable(dsi);
	640	+
	641	+ if (dsi->driver_data->has_shadow_ctl)
	642	+ writel(FORCE_COMMIT \| BYPASS_SHADOW,
	643	+ dsi->regs + DSI_SHADOW_DEBUG);
	644	+
593	645	mtk_dsi_reset_engine(dsi);
594	646	mtk_dsi_phy_timconfig(dsi);
595	647
596		- mtk_dsi_rxtx_control(dsi);
597	648	mtk_dsi_ps_control_vact(dsi);
598	649	mtk_dsi_set_vm_cmd(dsi);
599	650	mtk_dsi_config_vdo_timing(dsi);
600	651	mtk_dsi_set_interrupt_enable(dsi);
601	652
602		- mtk_dsi_clk_ulp_mode_leave(dsi);
603		- mtk_dsi_lane0_ulp_mode_leave(dsi);
604		- mtk_dsi_clk_hs_mode(dsi, 0);
605		-
606		- if (dsi->panel) {
607		- if (drm_panel_prepare(dsi->panel)) {
608		- DRM_ERROR("failed to prepare the panel\n");
609		- goto err_disable_digital_clk;
610		- }
611		- }
612		-
613	653	return 0;
614		-err_disable_digital_clk:
615		- clk_disable_unprepare(dsi->digital_clk);
616	654	err_disable_engine_clk:
617	655	clk_disable_unprepare(dsi->engine_clk);
618	656	err_phy_power_off:
..	..	@@ -639,18 +677,12 @@
639	677	*/
640	678	mtk_dsi_stop(dsi);
641	679
642		- if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
643		- if (dsi->panel) {
644		- if (drm_panel_unprepare(dsi->panel)) {
645		- DRM_ERROR("failed to unprepare the panel\n");
646		- return;
647		- }
648		- }
649		- }
650		-
	680	+ mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
651	681	mtk_dsi_reset_engine(dsi);
652	682	mtk_dsi_lane0_ulp_mode_enter(dsi);
653	683	mtk_dsi_clk_ulp_mode_enter(dsi);
	684	+ /* set the lane number as 0 to pull down mipi */
	685	+ writel(0, dsi->regs + DSI_TXRX_CTRL);
654	686
655	687	mtk_dsi_disable(dsi);
656	688
..	..	@@ -658,39 +690,37 @@
658	690	clk_disable_unprepare(dsi->digital_clk);
659	691
660	692	phy_power_off(dsi->phy);
	693	+
	694	+ dsi->lanes_ready = false;
	695	+}
	696	+
	697	+static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
	698	+{
	699	+ if (!dsi->lanes_ready) {
	700	+ dsi->lanes_ready = true;
	701	+ mtk_dsi_rxtx_control(dsi);
	702	+ usleep_range(30, 100);
	703	+ mtk_dsi_reset_dphy(dsi);
	704	+ mtk_dsi_clk_ulp_mode_leave(dsi);
	705	+ mtk_dsi_lane0_ulp_mode_leave(dsi);
	706	+ mtk_dsi_clk_hs_mode(dsi, 0);
	707	+ usleep_range(1000, 3000);
	708	+ /* The reaction time after pulling up the mipi signal for dsi_rx */
	709	+ }
661	710	}
662	711
663	712	static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
664	713	{
665		- int ret;
666		-
667	714	if (dsi->enabled)
668	715	return;
669	716
670		- ret = mtk_dsi_poweron(dsi);
671		- if (ret < 0) {
672		- DRM_ERROR("failed to power on dsi\n");
673		- return;
674		- }
675		-
	717	+ mtk_dsi_lane_ready(dsi);
676	718	mtk_dsi_set_mode(dsi);
677	719	mtk_dsi_clk_hs_mode(dsi, 1);
678	720
679	721	mtk_dsi_start(dsi);
680	722
681		- if (dsi->panel) {
682		- if (drm_panel_enable(dsi->panel)) {
683		- DRM_ERROR("failed to enable the panel\n");
684		- goto err_dsi_power_off;
685		- }
686		- }
687		-
688	723	dsi->enabled = true;
689		-
690		- return;
691		-err_dsi_power_off:
692		- mtk_dsi_stop(dsi);
693		- mtk_dsi_poweroff(dsi);
694	724	}
695	725
696	726	static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
..	..	@@ -698,160 +728,77 @@
698	728	if (!dsi->enabled)
699	729	return;
700	730
701		- if (dsi->panel) {
702		- if (drm_panel_disable(dsi->panel)) {
703		- DRM_ERROR("failed to disable the panel\n");
704		- return;
705		- }
706		- }
707		-
708		- mtk_dsi_poweroff(dsi);
709		-
710	731	dsi->enabled = false;
711	732	}
712	733
713		-static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
	734	+static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
	735	+ enum drm_bridge_attach_flags flags)
714	736	{
715		- drm_encoder_cleanup(encoder);
	737	+ struct mtk_dsi *dsi = bridge_to_dsi(bridge);
	738	+
	739	+ /* Attach the panel or bridge to the dsi bridge */
	740	+ return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
	741	+ &dsi->bridge, flags);
716	742	}
717	743
718		-static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
719		- .destroy = mtk_dsi_encoder_destroy,
720		-};
721		-
722		-static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
723		- const struct drm_display_mode *mode,
724		- struct drm_display_mode *adjusted_mode)
	744	+static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
	745	+ const struct drm_display_mode *mode,
	746	+ const struct drm_display_mode *adjusted)
725	747	{
726		- return true;
727		-}
728		-
729		-static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
730		- struct drm_display_mode *mode,
731		- struct drm_display_mode *adjusted)
732		-{
733		- struct mtk_dsi *dsi = encoder_to_dsi(encoder);
	748	+ struct mtk_dsi *dsi = bridge_to_dsi(bridge);
734	749
735	750	drm_display_mode_to_videomode(adjusted, &dsi->vm);
736	751	}
737	752
738		-static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
	753	+static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
	754	+ struct drm_bridge_state *old_bridge_state)
739	755	{
740		- struct mtk_dsi *dsi = encoder_to_dsi(encoder);
	756	+ struct mtk_dsi *dsi = bridge_to_dsi(bridge);
741	757
742	758	mtk_output_dsi_disable(dsi);
743	759	}
744	760
745		-static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
	761	+static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
	762	+ struct drm_bridge_state *old_bridge_state)
746	763	{
747		- struct mtk_dsi *dsi = encoder_to_dsi(encoder);
	764	+ struct mtk_dsi *dsi = bridge_to_dsi(bridge);
	765	+
	766	+ if (dsi->refcount == 0)
	767	+ return;
748	768
749	769	mtk_output_dsi_enable(dsi);
750	770	}
751	771
752		-static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
	772	+static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
	773	+ struct drm_bridge_state *old_bridge_state)
753	774	{
754		- struct mtk_dsi *dsi = connector_to_dsi(connector);
755		-
756		- return drm_panel_get_modes(dsi->panel);
757		-}
758		-
759		-static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
760		- .mode_fixup = mtk_dsi_encoder_mode_fixup,
761		- .mode_set = mtk_dsi_encoder_mode_set,
762		- .disable = mtk_dsi_encoder_disable,
763		- .enable = mtk_dsi_encoder_enable,
764		-};
765		-
766		-static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
767		- .fill_modes = drm_helper_probe_single_connector_modes,
768		- .destroy = drm_connector_cleanup,
769		- .reset = drm_atomic_helper_connector_reset,
770		- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
771		- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
772		-};
773		-
774		-static const struct drm_connector_helper_funcs
775		- mtk_dsi_connector_helper_funcs = {
776		- .get_modes = mtk_dsi_connector_get_modes,
777		-};
778		-
779		-static int mtk_dsi_create_connector(struct drm_device drm, struct mtk_dsi dsi)
780		-{
	775	+ struct mtk_dsi *dsi = bridge_to_dsi(bridge);
781	776	int ret;
782	777
783		- ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
784		- DRM_MODE_CONNECTOR_DSI);
785		- if (ret) {
786		- DRM_ERROR("Failed to connector init to drm\n");
787		- return ret;
788		- }
789		-
790		- drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
791		-
792		- dsi->conn.dpms = DRM_MODE_DPMS_OFF;
793		- drm_connector_attach_encoder(&dsi->conn, &dsi->encoder);
794		-
795		- if (dsi->panel) {
796		- ret = drm_panel_attach(dsi->panel, &dsi->conn);
797		- if (ret) {
798		- DRM_ERROR("Failed to attach panel to drm\n");
799		- goto err_connector_cleanup;
800		- }
801		- }
802		-
803		- return 0;
804		-
805		-err_connector_cleanup:
806		- drm_connector_cleanup(&dsi->conn);
807		- return ret;
	778	+ ret = mtk_dsi_poweron(dsi);
	779	+ if (ret < 0)
	780	+ DRM_ERROR("failed to power on dsi\n");
808	781	}
809	782
810		-static int mtk_dsi_create_conn_enc(struct drm_device drm, struct mtk_dsi dsi)
	783	+static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
	784	+ struct drm_bridge_state *old_bridge_state)
811	785	{
812		- int ret;
	786	+ struct mtk_dsi *dsi = bridge_to_dsi(bridge);
813	787
814		- ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
815		- DRM_MODE_ENCODER_DSI, NULL);
816		- if (ret) {
817		- DRM_ERROR("Failed to encoder init to drm\n");
818		- return ret;
819		- }
820		- drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
821		-
822		- /*
823		- * Currently display data paths are statically assigned to a crtc each.
824		- * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
825		- */
826		- dsi->encoder.possible_crtcs = 1;
827		-
828		- /* If there's a bridge, attach to it and let it create the connector */
829		- ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
830		- if (ret) {
831		- DRM_ERROR("Failed to attach bridge to drm\n");
832		-
833		- /* Otherwise create our own connector and attach to a panel */
834		- ret = mtk_dsi_create_connector(drm, dsi);
835		- if (ret)
836		- goto err_encoder_cleanup;
837		- }
838		-
839		- return 0;
840		-
841		-err_encoder_cleanup:
842		- drm_encoder_cleanup(&dsi->encoder);
843		- return ret;
	788	+ mtk_dsi_poweroff(dsi);
844	789	}
845	790
846		-static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
847		-{
848		- drm_encoder_cleanup(&dsi->encoder);
849		- /* Skip connector cleanup if creation was delegated to the bridge */
850		- if (dsi->conn.dev)
851		- drm_connector_cleanup(&dsi->conn);
852		- if (dsi->panel)
853		- drm_panel_detach(dsi->panel);
854		-}
	791	+static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
	792	+ .attach = mtk_dsi_bridge_attach,
	793	+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
	794	+ .atomic_disable = mtk_dsi_bridge_atomic_disable,
	795	+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
	796	+ .atomic_enable = mtk_dsi_bridge_atomic_enable,
	797	+ .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
	798	+ .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
	799	+ .atomic_reset = drm_atomic_helper_bridge_reset,
	800	+ .mode_set = mtk_dsi_bridge_mode_set,
	801	+};
855	802
856	803	static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
857	804	{
..	..	@@ -880,20 +827,6 @@
880	827	dsi->lanes = device->lanes;
881	828	dsi->format = device->format;
882	829	dsi->mode_flags = device->mode_flags;
883		-
884		- if (dsi->conn.dev)
885		- drm_helper_hpd_irq_event(dsi->conn.dev);
886		-
887		- return 0;
888		-}
889		-
890		-static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
891		- struct mipi_dsi_device *device)
892		-{
893		- struct mtk_dsi *dsi = host_to_dsi(host);
894		-
895		- if (dsi->conn.dev)
896		- drm_helper_hpd_irq_event(dsi->conn.dev);
897	830
898	831	return 0;
899	832	}
..	..	@@ -941,6 +874,7 @@
941	874	const char *tx_buf = msg->tx_buf;
942	875	u8 config, cmdq_size, cmdq_off, type = msg->type;
943	876	u32 reg_val, cmdq_mask, i;
	877	+ u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
944	878
945	879	if (MTK_DSI_HOST_IS_READ(type))
946	880	config = BTA;
..	..	@@ -960,9 +894,11 @@
960	894	}
961	895
962	896	for (i = 0; i < msg->tx_len; i++)
963		- writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
	897	+ mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
	898	+ (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
	899	+ tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
964	900
965		- mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
	901	+ mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
966	902	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
967	903	}
968	904
..	..	@@ -988,24 +924,35 @@
988	924	u8 read_data[16];
989	925	void *src_addr;
990	926	u8 irq_flag = CMD_DONE_INT_FLAG;
	927	+ u32 dsi_mode;
	928	+ int ret;
991	929
992		- if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
993		- DRM_ERROR("dsi engine is not command mode\n");
994		- return -EINVAL;
	930	+ dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
	931	+ if (dsi_mode & MODE) {
	932	+ mtk_dsi_stop(dsi);
	933	+ ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
	934	+ if (ret)
	935	+ goto restore_dsi_mode;
995	936	}
996	937
997	938	if (MTK_DSI_HOST_IS_READ(msg->type))
998	939	irq_flag \|= LPRX_RD_RDY_INT_FLAG;
999	940
1000		- if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
1001		- return -ETIME;
	941	+ mtk_dsi_lane_ready(dsi);
1002	942
1003		- if (!MTK_DSI_HOST_IS_READ(msg->type))
1004		- return 0;
	943	+ ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
	944	+ if (ret)
	945	+ goto restore_dsi_mode;
	946	+
	947	+ if (!MTK_DSI_HOST_IS_READ(msg->type)) {
	948	+ recv_cnt = 0;
	949	+ goto restore_dsi_mode;
	950	+ }
1005	951
1006	952	if (!msg->rx_buf) {
1007	953	DRM_ERROR("dsi receive buffer size may be NULL\n");
1008		- return -EINVAL;
	954	+ ret = -EINVAL;
	955	+ goto restore_dsi_mode;
1009	956	}
1010	957
1011	958	for (i = 0; i < 16; i++)
..	..	@@ -1030,14 +977,52 @@
1030	977	DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1031	978	recv_cnt, ((u8 )(msg->tx_buf)));
1032	979
1033		- return recv_cnt;
	980	+restore_dsi_mode:
	981	+ if (dsi_mode & MODE) {
	982	+ mtk_dsi_set_mode(dsi);
	983	+ mtk_dsi_start(dsi);
	984	+ }
	985	+
	986	+ return ret < 0 ? ret : recv_cnt;
1034	987	}
1035	988
1036	989	static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1037	990	.attach = mtk_dsi_host_attach,
1038		- .detach = mtk_dsi_host_detach,
1039	991	.transfer = mtk_dsi_host_transfer,
1040	992	};
	993	+
	994	+static int mtk_dsi_encoder_init(struct drm_device drm, struct mtk_dsi dsi)
	995	+{
	996	+ int ret;
	997	+
	998	+ ret = drm_simple_encoder_init(drm, &dsi->encoder,
	999	+ DRM_MODE_ENCODER_DSI);
	1000	+ if (ret) {
	1001	+ DRM_ERROR("Failed to encoder init to drm\n");
	1002	+ return ret;
	1003	+ }
	1004	+
	1005	+ dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
	1006	+
	1007	+ ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
	1008	+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
	1009	+ if (ret)
	1010	+ goto err_cleanup_encoder;
	1011	+
	1012	+ dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
	1013	+ if (IS_ERR(dsi->connector)) {
	1014	+ DRM_ERROR("Unable to create bridge connector\n");
	1015	+ ret = PTR_ERR(dsi->connector);
	1016	+ goto err_cleanup_encoder;
	1017	+ }
	1018	+ drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
	1019	+
	1020	+ return 0;
	1021	+
	1022	+err_cleanup_encoder:
	1023	+ drm_encoder_cleanup(&dsi->encoder);
	1024	+ return ret;
	1025	+}
1041	1026
1042	1027	static int mtk_dsi_bind(struct device dev, struct device master, void *data)
1043	1028	{
..	..	@@ -1052,23 +1037,13 @@
1052	1037	return ret;
1053	1038	}
1054	1039
1055		- ret = mipi_dsi_host_register(&dsi->host);
1056		- if (ret < 0) {
1057		- dev_err(dev, "failed to register DSI host: %d\n", ret);
1058		- goto err_ddp_comp_unregister;
1059		- }
1060		-
1061		- ret = mtk_dsi_create_conn_enc(drm, dsi);
1062		- if (ret) {
1063		- DRM_ERROR("Encoder create failed with %d\n", ret);
	1040	+ ret = mtk_dsi_encoder_init(drm, dsi);
	1041	+ if (ret)
1064	1042	goto err_unregister;
1065		- }
1066	1043
1067	1044	return 0;
1068	1045
1069	1046	err_unregister:
1070		- mipi_dsi_host_unregister(&dsi->host);
1071		-err_ddp_comp_unregister:
1072	1047	mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1073	1048	return ret;
1074	1049	}
..	..	@@ -1079,8 +1054,7 @@
1079	1054	struct drm_device *drm = data;
1080	1055	struct mtk_dsi *dsi = dev_get_drvdata(dev);
1081	1056
1082		- mtk_dsi_destroy_conn_enc(dsi);
1083		- mipi_dsi_host_unregister(&dsi->host);
	1057	+ drm_encoder_cleanup(&dsi->encoder);
1084	1058	mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1085	1059	}
1086	1060
..	..	@@ -1093,6 +1067,7 @@
1093	1067	{
1094	1068	struct mtk_dsi *dsi;
1095	1069	struct device *dev = &pdev->dev;
	1070	+ struct drm_panel *panel;
1096	1071	struct resource *regs;
1097	1072	int irq_num;
1098	1073	int comp_id;
..	..	@@ -1104,31 +1079,50 @@
1104	1079
1105	1080	dsi->host.ops = &mtk_dsi_ops;
1106	1081	dsi->host.dev = dev;
	1082	+ ret = mipi_dsi_host_register(&dsi->host);
	1083	+ if (ret < 0) {
	1084	+ dev_err(dev, "failed to register DSI host: %d\n", ret);
	1085	+ return ret;
	1086	+ }
1107	1087
1108	1088	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1109		- &dsi->panel, &dsi->bridge);
	1089	+ &panel, &dsi->next_bridge);
1110	1090	if (ret)
1111		- return ret;
	1091	+ goto err_unregister_host;
	1092	+
	1093	+ if (panel) {
	1094	+ dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel);
	1095	+ if (IS_ERR(dsi->next_bridge)) {
	1096	+ ret = PTR_ERR(dsi->next_bridge);
	1097	+ goto err_unregister_host;
	1098	+ }
	1099	+ }
	1100	+
	1101	+ dsi->driver_data = of_device_get_match_data(dev);
1112	1102
1113	1103	dsi->engine_clk = devm_clk_get(dev, "engine");
1114	1104	if (IS_ERR(dsi->engine_clk)) {
1115	1105	ret = PTR_ERR(dsi->engine_clk);
1116		- dev_err(dev, "Failed to get engine clock: %d\n", ret);
1117		- return ret;
	1106	+
	1107	+ if (ret != -EPROBE_DEFER)
	1108	+ dev_err(dev, "Failed to get engine clock: %d\n", ret);
	1109	+ goto err_unregister_host;
1118	1110	}
1119	1111
1120	1112	dsi->digital_clk = devm_clk_get(dev, "digital");
1121	1113	if (IS_ERR(dsi->digital_clk)) {
1122	1114	ret = PTR_ERR(dsi->digital_clk);
1123		- dev_err(dev, "Failed to get digital clock: %d\n", ret);
1124		- return ret;
	1115	+
	1116	+ if (ret != -EPROBE_DEFER)
	1117	+ dev_err(dev, "Failed to get digital clock: %d\n", ret);
	1118	+ goto err_unregister_host;
1125	1119	}
1126	1120
1127	1121	dsi->hs_clk = devm_clk_get(dev, "hs");
1128	1122	if (IS_ERR(dsi->hs_clk)) {
1129	1123	ret = PTR_ERR(dsi->hs_clk);
1130	1124	dev_err(dev, "Failed to get hs clock: %d\n", ret);
1131		- return ret;
	1125	+ goto err_unregister_host;
1132	1126	}
1133	1127
1134	1128	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
..	..	@@ -1136,33 +1130,35 @@
1136	1130	if (IS_ERR(dsi->regs)) {
1137	1131	ret = PTR_ERR(dsi->regs);
1138	1132	dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1139		- return ret;
	1133	+ goto err_unregister_host;
1140	1134	}
1141	1135
1142	1136	dsi->phy = devm_phy_get(dev, "dphy");
1143	1137	if (IS_ERR(dsi->phy)) {
1144	1138	ret = PTR_ERR(dsi->phy);
1145	1139	dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1146		- return ret;
	1140	+ goto err_unregister_host;
1147	1141	}
1148	1142
1149	1143	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1150	1144	if (comp_id < 0) {
1151	1145	dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1152		- return comp_id;
	1146	+ ret = comp_id;
	1147	+ goto err_unregister_host;
1153	1148	}
1154	1149
1155	1150	ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1156	1151	&mtk_dsi_funcs);
1157	1152	if (ret) {
1158	1153	dev_err(dev, "Failed to initialize component: %d\n", ret);
1159		- return ret;
	1154	+ goto err_unregister_host;
1160	1155	}
1161	1156
1162	1157	irq_num = platform_get_irq(pdev, 0);
1163	1158	if (irq_num < 0) {
1164		- dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1165		- return -EPROBE_DEFER;
	1159	+ dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
	1160	+ ret = irq_num;
	1161	+ goto err_unregister_host;
1166	1162	}
1167	1163
1168	1164	irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
..	..	@@ -1170,14 +1166,30 @@
1170	1166	IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1171	1167	if (ret) {
1172	1168	dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1173		- return -EPROBE_DEFER;
	1169	+ goto err_unregister_host;
1174	1170	}
1175	1171
1176	1172	init_waitqueue_head(&dsi->irq_wait_queue);
1177	1173
1178	1174	platform_set_drvdata(pdev, dsi);
1179	1175
1180		- return component_add(&pdev->dev, &mtk_dsi_component_ops);
	1176	+ dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
	1177	+ dsi->bridge.of_node = dev->of_node;
	1178	+ dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
	1179	+
	1180	+ drm_bridge_add(&dsi->bridge);
	1181	+
	1182	+ ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
	1183	+ if (ret) {
	1184	+ dev_err(&pdev->dev, "failed to add component: %d\n", ret);
	1185	+ goto err_unregister_host;
	1186	+ }
	1187	+
	1188	+ return 0;
	1189	+
	1190	+err_unregister_host:
	1191	+ mipi_dsi_host_unregister(&dsi->host);
	1192	+ return ret;
1181	1193	}
1182	1194
1183	1195	static int mtk_dsi_remove(struct platform_device *pdev)
..	..	@@ -1185,14 +1197,34 @@
1185	1197	struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1186	1198
1187	1199	mtk_output_dsi_disable(dsi);
	1200	+ drm_bridge_remove(&dsi->bridge);
1188	1201	component_del(&pdev->dev, &mtk_dsi_component_ops);
	1202	+ mipi_dsi_host_unregister(&dsi->host);
1189	1203
1190	1204	return 0;
1191	1205	}
1192	1206
	1207	+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
	1208	+ .reg_cmdq_off = 0x200,
	1209	+};
	1210	+
	1211	+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
	1212	+ .reg_cmdq_off = 0x180,
	1213	+};
	1214	+
	1215	+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
	1216	+ .reg_cmdq_off = 0x200,
	1217	+ .has_shadow_ctl = true,
	1218	+ .has_size_ctl = true,
	1219	+};
	1220	+
1193	1221	static const struct of_device_id mtk_dsi_of_match[] = {
1194		- { .compatible = "mediatek,mt2701-dsi" },
1195		- { .compatible = "mediatek,mt8173-dsi" },
	1222	+ { .compatible = "mediatek,mt2701-dsi",
	1223	+ .data = &mt2701_dsi_driver_data },
	1224	+ { .compatible = "mediatek,mt8173-dsi",
	1225	+ .data = &mt8173_dsi_driver_data },
	1226	+ { .compatible = "mediatek,mt8183-dsi",
	1227	+ .data = &mt8183_dsi_driver_data },
1196	1228	{ },
1197	1229	};
1198	1230