| .. | .. |
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| 15 | 15 | #include <drm/drm_atomic_helper.h> |
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| 16 | 16 | #include <drm/drm_crtc_helper.h> |
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| 17 | 17 | #include <drm/drm_of.h> |
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| 18 | | -#include <drm/drmP.h> |
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| 18 | +#include <drm/drm_probe_helper.h> |
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| 19 | 19 | |
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| 20 | 20 | #include "../rockchip/rockchip_drm_drv.h" |
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| 21 | 21 | |
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| .. | .. |
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| 24 | 24 | 816, 864, 0, 576, 580, 586, 625, 0, |
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| 25 | 25 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | |
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| 26 | 26 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
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| 27 | | - .vrefresh = 50, 0, }, |
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| 27 | + 0, }, |
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| 28 | 28 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753, |
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| 29 | 29 | 815, 858, 0, 480, 483, 489, 525, 0, |
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| 30 | 30 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | |
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| 31 | 31 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
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| 32 | | - .vrefresh = 60, 0, }, |
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| 32 | + 0, }, |
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| 33 | 33 | }; |
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| 34 | 34 | |
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| 35 | 35 | struct rk630_tve { |
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| .. | .. |
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| 59 | 59 | }; |
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| 60 | 60 | |
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| 61 | 61 | static struct env_config ntsc_bt656_config[] = { |
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| 62 | + { BT656_DECODER_CTRL, 0x00000001 }, |
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| 62 | 63 | { BT656_DECODER_CROP, 0x00000000 }, |
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| 63 | 64 | { BT656_DECODER_SIZE, 0x01e002d0 }, |
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| 64 | 65 | { BT656_DECODER_HTOTAL_HS_END, 0x035a003e }, |
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| .. | .. |
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| 66 | 67 | { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 }, |
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| 67 | 68 | { BT656_DECODER_VS_ST_END_F1, 0x01060109 }, |
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| 68 | 69 | { BT656_DECODER_DBG_REG, 0x024002d0 }, |
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| 69 | | - { BT656_DECODER_CTRL, 0x00000001 }, |
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| 70 | 70 | }; |
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| 71 | 71 | |
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| 72 | 72 | static struct env_config ntsc_tve_config[] = { |
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| .. | .. |
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| 100 | 100 | }; |
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| 101 | 101 | |
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| 102 | 102 | static struct env_config pal_bt656_config[] = { |
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| 103 | + { BT656_DECODER_CTRL, 0x00000001 }, |
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| 103 | 104 | { BT656_DECODER_CROP, 0x00000000 }, |
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| 104 | 105 | { BT656_DECODER_SIZE, 0x024002d0 }, |
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| 105 | 106 | { BT656_DECODER_HTOTAL_HS_END, 0x0360003f }, |
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| .. | .. |
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| 107 | 108 | { BT656_DECODER_VTOTAL_VS_END, 0x02710003 }, |
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| 108 | 109 | { BT656_DECODER_VS_ST_END_F1, 0x0138013b }, |
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| 109 | 110 | { BT656_DECODER_DBG_REG, 0x024002d0 }, |
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| 110 | | - { BT656_DECODER_CTRL, 0x00000001 }, |
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| 111 | 111 | }; |
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| 112 | 112 | |
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| 113 | 113 | static struct env_config pal_tve_config[] = { |
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| .. | .. |
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| 125 | 125 | { TVE_LUMA_FILTER7, 0x0ffa0e43 }, |
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| 126 | 126 | { TVE_LUMA_FILTER8, 0x08200527 }, |
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| 127 | 127 | { TVE_IMAGE_POSITION, 0x001500f6 }, |
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| 128 | | - { TVE_ROUTING, 0x10008882 }, |
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| 128 | + { TVE_ROUTING, 0x1000088a }, |
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| 129 | 129 | { TVE_SYNC_ADJUST, 0x00000000 }, |
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| 130 | 130 | { TVE_STATUS, 0x000000b0 }, |
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| 131 | 131 | { TVE_CTRL, 0x00000000 }, |
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| 132 | 132 | { TVE_INTR_STATUS, 0x00000000 }, |
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| 133 | 133 | { TVE_INTR_EN, 0x00000000 }, |
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| 134 | 134 | { TVE_INTR_CLR, 0x00000000 }, |
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| 135 | | - { TVE_COLOR_BUSRT_SAT, 0x00366044 }, |
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| 135 | + { TVE_COLOR_BUSRT_SAT, 0x002e553c }, |
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| 136 | 136 | { TVE_CHROMA_BANDWIDTH, 0x00000022 }, |
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| 137 | | - { TVE_BRIGHTNESS_CONTRAST, 0x0000a300 }, |
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| 137 | + { TVE_BRIGHTNESS_CONTRAST, 0x00008900 }, |
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| 138 | 138 | { TVE_ID, 0x0a010000 }, |
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| 139 | 139 | { TVE_REVISION, 0x00010108 }, |
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| 140 | 140 | { TVE_CLAMP, 0x00000000 }, |
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| .. | .. |
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| 164 | 164 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
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| 165 | 165 | .rd_table = &rk630_tve_readable_table, |
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| 166 | 166 | }; |
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| 167 | +EXPORT_SYMBOL_GPL(rk630_tve_regmap_config); |
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| 167 | 168 | |
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| 168 | 169 | static struct rk630_tve *bridge_to_tve(struct drm_bridge *bridge) |
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| 169 | 170 | { |
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| .. | .. |
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| 194 | 195 | { |
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| 195 | 196 | int ret; |
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| 196 | 197 | struct env_config *bt656_cfg, *tve_cfg; |
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| 197 | | - int upsample_en = tve->is_4x ? 1 : 0; |
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| 198 | 198 | |
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| 199 | 199 | switch (tve->mode) { |
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| 200 | 200 | case CVBS_PAL: |
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| .. | .. |
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| 225 | 225 | SW_DCLK_UPSAMPLE_EN_MASK | |
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| 226 | 226 | SW_TVE_MODE_MASK | SW_TVE_EN_MASK, |
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| 227 | 227 | SW_TVE_DCLK_POL(0) | SW_TVE_DCLK_EN(1) | |
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| 228 | | - SW_DCLK_UPSAMPLE_EN(upsample_en) | |
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| 228 | + SW_DCLK_UPSAMPLE_EN(tve->is_4x) | |
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| 229 | 229 | SW_TVE_MODE(1) | SW_TVE_EN(1)); |
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| 230 | 230 | else |
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| 231 | 231 | regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON0, |
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| .. | .. |
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| 234 | 234 | SW_DCLK_UPSAMPLE_EN_MASK | |
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| 235 | 235 | SW_TVE_MODE_MASK | SW_TVE_EN_MASK, |
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| 236 | 236 | SW_TVE_DCLK_POL(0) | SW_TVE_DCLK_EN(1) | |
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| 237 | | - SW_DCLK_UPSAMPLE_EN(upsample_en) | |
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| 237 | + SW_DCLK_UPSAMPLE_EN(tve->is_4x) | |
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| 238 | 238 | SW_TVE_MODE(0) | SW_TVE_EN(1)); |
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| 239 | | - |
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| 240 | | - regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, |
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| 241 | | - DCLK_UPSAMPLE_2X4X_MASK, |
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| 242 | | - DCLK_UPSAMPLE_2X4X(tve->is_4x - 1)); |
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| 243 | 239 | |
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| 244 | 240 | ret = rk630_tve_write_block(tve, tve_cfg, 27); |
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| 245 | 241 | if (ret < 0) { |
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| .. | .. |
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| 260 | 256 | |
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| 261 | 257 | static int rk630_tve_enable(struct rk630_tve *tve) |
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| 262 | 258 | { |
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| 263 | | - int ret; |
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| 259 | + int ret, i; |
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| 260 | + u32 val = 0; |
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| 264 | 261 | |
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| 265 | 262 | dev_dbg(tve->dev, "%s\n", __func__); |
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| 266 | 263 | |
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| 267 | 264 | /* config bt656 input gpio*/ |
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| 268 | 265 | regmap_write(tve->grf, PLUMAGE_GRF_GPIO0A_IOMUX, 0x55555555); |
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| 269 | 266 | |
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| 270 | | - regmap_update_bits(tve->grf, PLUMAGE_GRF_GPIO0B_IOMUX, PIN0_SEL_MASK, |
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| 271 | | - PIN0_SEL(1)); |
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| 267 | + regmap_update_bits(tve->grf, PLUMAGE_GRF_GPIO0B_IOMUX, GPIO0B0_SEL_MASK, |
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| 268 | + GPIO0B0_SEL(1)); |
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| 272 | 269 | |
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| 273 | 270 | regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, VDAC_ENDAC0_MASK, |
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| 274 | 271 | VDAC_ENDAC0(0)); |
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| .. | .. |
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| 279 | 276 | |
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| 280 | 277 | /*config clk*/ |
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| 281 | 278 | if (!tve->is_4x) { |
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| 282 | | - regmap_update_bits(tve->cru, CRU_GATE_CON0, |
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| 283 | | - DCLK_CVBS_4X_PLL_CLK_GATE_MASK, |
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| 284 | | - DCLK_CVBS_4X_PLL_CLK_GATE(1)); |
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| 279 | + regmap_update_bits(tve->cru, CRU_MODE_CON, CLK_SPLL_MODE_MASK, |
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| 280 | + CLK_SPLL_MODE(2)); |
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| 285 | 281 | } else { |
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| 286 | | - regmap_update_bits(tve->cru, CRU_CLKSEL_CON1, |
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| 287 | | - DCLK_CVBS_4X_DIV_CON_MASK, |
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| 288 | | - DCLK_CVBS_4X_DIV_CON(0)); |
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| 282 | + regmap_update_bits(tve->cru, CRU_SPLL_CON1, PLLPD0_MASK, |
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| 283 | + PLLPD0(1)); |
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| 289 | 284 | |
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| 290 | | - regmap_update_bits(tve->cru, CRU_GATE_CON0, |
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| 291 | | - DCLK_CVBS_4X_PLL_CLK_GATE_MASK, |
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| 292 | | - DCLK_CVBS_4X_PLL_CLK_GATE(0)); |
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| 285 | + regmap_update_bits(tve->cru, CRU_MODE_CON, CLK_SPLL_MODE_MASK, |
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| 286 | + CLK_SPLL_MODE(1)); |
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| 287 | + |
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| 288 | + regmap_update_bits(tve->cru, CRU_SPLL_CON1, PLLPD0_MASK, |
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| 289 | + PLLPD0(0)); |
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| 290 | + |
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| 291 | + for (i = 0; i < 10; i++) { |
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| 292 | + usleep_range(1000, 2000); |
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| 293 | + regmap_read(tve->cru, CRU_SPLL_CON1, &val); |
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| 294 | + if (val & PLL_LOCK) { |
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| 295 | + dev_dbg(tve->dev, "rk630 pll locked\n"); |
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| 296 | + break; |
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| 297 | + } |
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| 298 | + } |
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| 299 | + if (!(val & PLL_LOCK)) { |
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| 300 | + dev_err(tve->dev, "rk630 pll unlock\n"); |
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| 301 | + return -EINVAL; |
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| 302 | + } |
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| 293 | 303 | } |
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| 294 | | - |
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| 295 | | - /* set vdac gain */ |
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| 296 | | - regmap_write(tve->grf, PLUMAGE_GRF_SOC_CON3, 0x003f003f); |
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| 297 | 304 | |
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| 298 | 305 | /* enable vdac */ |
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| 299 | 306 | regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, |
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| .. | .. |
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| 369 | 376 | |
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| 370 | 377 | static void |
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| 371 | 378 | rk630_tve_bridge_mode_set(struct drm_bridge *bridge, |
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| 372 | | - struct drm_display_mode *mode, |
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| 373 | | - struct drm_display_mode *adjusted_mode) |
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| 379 | + const struct drm_display_mode *mode, |
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| 380 | + const struct drm_display_mode *adjusted_mode) |
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| 374 | 381 | { |
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| 375 | 382 | struct rk630_tve *tve; |
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| 376 | 383 | |
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| .. | .. |
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| 401 | 408 | rk630_tve_disable(tve); |
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| 402 | 409 | } |
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| 403 | 410 | |
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| 404 | | -static int rk630_tve_bridge_attach(struct drm_bridge *bridge) |
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| 411 | +static int rk630_tve_bridge_attach(struct drm_bridge *bridge, |
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| 412 | + enum drm_bridge_attach_flags flags) |
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| 405 | 413 | { |
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| 406 | 414 | struct rk630_tve *tve = bridge_to_tve(bridge); |
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| 407 | 415 | int ret; |
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| .. | .. |
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| 455 | 463 | struct rk630 *rk630 = dev_get_drvdata(pdev->dev.parent); |
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| 456 | 464 | struct rk630_tve *tve; |
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| 457 | 465 | struct device *dev = &pdev->dev; |
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| 458 | | - int ret; |
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| 459 | 466 | |
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| 460 | 467 | if (!of_device_is_available(dev->of_node)) |
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| 461 | 468 | return -ENODEV; |
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| .. | .. |
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| 473 | 480 | tve->tvemap = rk630->tve; |
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| 474 | 481 | if (!tve->grf | !tve->cru | !tve->tvemap) |
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| 475 | 482 | return -ENODEV; |
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| 476 | | - |
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| 477 | | - ret = device_property_read_u32(dev, "rockchip,tve-upsample", |
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| 478 | | - &tve->is_4x); |
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| 479 | | - if (ret < 0) |
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| 480 | | - tve->is_4x = 0; |
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| 481 | 483 | |
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| 482 | 484 | tve->mode = CVBS_PAL; |
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| 483 | 485 | |
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