change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
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@@ -83,10 +83,10 @@
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 	union {
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 		struct {
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-		uint32_t gds_heap_base:6;
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-		uint32_t reserved3:5;
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-		uint32_t gds_heap_size:6;
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-		uint32_t reserved4:15;
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+		uint32_t gds_heap_base:10;
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+		uint32_t reserved3:1;
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+		uint32_t gds_heap_size:10;
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+		uint32_t reserved4:11;
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 		} bitfields8;
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 		uint32_t ordinal8;
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 	};
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@@ -120,7 +120,7 @@
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 			uint32_t ib_size:20;
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 			uint32_t chain:1;
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 			uint32_t offload_polling:1;
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-			uint32_t reserved2:1;
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+			uint32_t chained_runlist_idle_disable:1;
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 			uint32_t valid:1;
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 			uint32_t process_cnt:4;
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 			uint32_t reserved3:4;
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@@ -176,11 +176,10 @@
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 	union {
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 		struct {
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-			uint32_t num_gws:6;
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-			uint32_t reserved7:1;
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+			uint32_t num_gws:7;
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 			uint32_t sdma_enable:1;
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 			uint32_t num_oac:4;
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-			uint32_t reserved8:4;
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+			uint32_t gds_size_hi:4;
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 			uint32_t gds_size:6;
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 			uint32_t num_queues:10;
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 		} bitfields14;
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@@ -255,17 +254,16 @@
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 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
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 };
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-enum mes_map_queues_alloc_format_enum {
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-	alloc_format__mes_map_queues__one_per_pipe_vi = 0,
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-alloc_format__mes_map_queues__all_on_one_pipe_vi = 1
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-};
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-
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 enum mes_map_queues_engine_sel_enum {
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 	engine_sel__mes_map_queues__compute_vi = 0,
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 	engine_sel__mes_map_queues__sdma0_vi = 2,
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 	engine_sel__mes_map_queues__sdma1_vi = 3
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 };
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+enum mes_map_queues_extended_engine_sel_enum {
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+	extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
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+	extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
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+};
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 struct pm4_mes_map_queues {
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 	union {
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@@ -275,11 +273,14 @@
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 	union {
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 		struct {
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-			uint32_t reserved1:4;
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+			uint32_t reserved1:2;
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+			enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2;
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 			enum mes_map_queues_queue_sel_enum queue_sel:2;
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-			uint32_t reserved2:15;
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+			uint32_t reserved5:6;
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+			uint32_t gws_control_queue:1;
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+			uint32_t reserved2:8;
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 			enum mes_map_queues_queue_type_enum queue_type:3;
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-			enum mes_map_queues_alloc_format_enum alloc_format:2;
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+			uint32_t reserved3:2;
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 			enum mes_map_queues_engine_sel_enum engine_sel:3;
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 			uint32_t num_queues:3;
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 		} bitfields2;
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@@ -386,6 +387,11 @@
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 	engine_sel__mes_unmap_queues__sdmal = 3
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 };
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+enum mes_unmap_queues_extended_engine_sel_enum {
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+	extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0,
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+	extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1
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+};
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+
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 struct pm4_mes_unmap_queues {
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 	union {
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 		union PM4_MES_TYPE_3_HEADER   header;            /* header */
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@@ -395,7 +401,7 @@
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 	union {
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 		struct {
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 			enum mes_unmap_queues_action_enum action:2;
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-			uint32_t reserved1:2;
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+			enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2;
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 			enum mes_unmap_queues_queue_sel_enum queue_sel:2;
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 			uint32_t reserved2:20;
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 			enum mes_unmap_queues_engine_sel_enum engine_sel:3;