change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/fpga/xilinx-spi.c
..
..
@@ -1,13 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * Xilinx Spartan6 Slave Serial SPI Driver
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+ * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
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  *
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  * Copyright (C) 2017 DENX Software Engineering
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  *
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  * Anatolij Gustschin <agust@denx.de>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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  *
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  * Manage Xilinx FPGA firmware that is loaded over SPI using
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  * the slave serial configuration interface.
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@@ -26,17 +23,72 @@
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 struct xilinx_spi_conf {
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 	struct spi_device *spi;
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 	struct gpio_desc *prog_b;
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+	struct gpio_desc *init_b;
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 	struct gpio_desc *done;
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 };
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29
 
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-static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
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+static int get_done_gpio(struct fpga_manager *mgr)
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 {
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 	struct xilinx_spi_conf *conf = mgr->priv;
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+	int ret;
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34
 
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-	if (!gpiod_get_value(conf->done))
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+	ret = gpiod_get_value(conf->done);
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+
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+	if (ret < 0)
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+		dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret);
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+
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+	return ret;
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+}
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+
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+static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
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+{
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+	if (!get_done_gpio(mgr))
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 		return FPGA_MGR_STATE_RESET;
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 	return FPGA_MGR_STATE_UNKNOWN;
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+}
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+
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+/**
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+ * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
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+ * a given delay if the pin is unavailable
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+ *
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+ * @mgr:        The FPGA manager object
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+ * @value:      Value INIT_B to wait for (1 = asserted = low)
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+ * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
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+ *
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+ * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
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+ * too much time passed waiting for that. If no INIT_B GPIO is available
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+ * then always return 0.
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+ */
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+static int wait_for_init_b(struct fpga_manager *mgr, int value,
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+			   unsigned long alt_udelay)
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+{
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+	struct xilinx_spi_conf *conf = mgr->priv;
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+	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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+
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+	if (conf->init_b) {
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+		while (time_before(jiffies, timeout)) {
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+			int ret = gpiod_get_value(conf->init_b);
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+
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+			if (ret == value)
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+				return 0;
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+
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+			if (ret < 0) {
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+				dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
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+				return ret;
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+			}
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+
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+			usleep_range(100, 400);
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+		}
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+
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+		dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
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+			value ? "assert" : "deassert");
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+		return -ETIMEDOUT;
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+	}
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+
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+	udelay(alt_udelay);
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+
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+	return 0;
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 }
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 static int xilinx_spi_write_init(struct fpga_manager *mgr,
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@@ -44,27 +96,34 @@
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 				 const char *buf, size_t count)
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 {
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 	struct xilinx_spi_conf *conf = mgr->priv;
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-	const size_t prog_latency_7500us = 7500;
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-	const size_t prog_pulse_1us = 1;
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+	int err;
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 	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
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-		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
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+		dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
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 		return -EINVAL;
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 	}
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 	gpiod_set_value(conf->prog_b, 1);
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-	udelay(prog_pulse_1us); /* min is 500 ns */
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+	err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
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+	if (err) {
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+		gpiod_set_value(conf->prog_b, 0);
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+		return err;
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+	}
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 	gpiod_set_value(conf->prog_b, 0);
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-	if (gpiod_get_value(conf->done)) {
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+	err = wait_for_init_b(mgr, 0, 0);
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+	if (err)
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+		return err;
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+
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+	if (get_done_gpio(mgr)) {
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 		dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
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 		return -EIO;
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 	}
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 	/* program latency */
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-	usleep_range(prog_latency_7500us, prog_latency_7500us + 100);
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+	usleep_range(7500, 7600);
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 	return 0;
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 }
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..
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@@ -111,25 +170,46 @@
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 				     struct fpga_image_info *info)
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 {
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 	struct xilinx_spi_conf *conf = mgr->priv;
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-	unsigned long timeout;
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+	unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
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+	bool expired = false;
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+	int done;
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 	int ret;
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-	if (gpiod_get_value(conf->done))
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-		return xilinx_spi_apply_cclk_cycles(conf);
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+	/*
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+	 * This loop is carefully written such that if the driver is
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+	 * scheduled out for more than 'timeout', we still check for DONE
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+	 * before giving up and we apply 8 extra CCLK cycles in all cases.
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+	 */
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+	while (!expired) {
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+		expired = time_after(jiffies, timeout);
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-	timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
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-
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-	while (time_before(jiffies, timeout)) {
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+		done = get_done_gpio(mgr);
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+		if (done < 0)
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+			return done;
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 		ret = xilinx_spi_apply_cclk_cycles(conf);
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 		if (ret)
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 			return ret;
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-		if (gpiod_get_value(conf->done))
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-			return xilinx_spi_apply_cclk_cycles(conf);
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+		if (done)
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+			return 0;
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 	}
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-	dev_err(&mgr->dev, "Timeout after config data transfer.\n");
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+	if (conf->init_b) {
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+		ret = gpiod_get_value(conf->init_b);
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+
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+		if (ret < 0) {
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+			dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
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+			return ret;
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+		}
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+
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+		dev_err(&mgr->dev,
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+			ret ? "CRC error or invalid device\n"
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+			: "Missing sync word or incomplete bitstream\n");
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+	} else {
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+		dev_err(&mgr->dev, "Timeout after config data transfer\n");
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+	}
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+
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 	return -ETIMEDOUT;
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 }
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..
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@@ -144,7 +224,6 @@
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 {
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 	struct xilinx_spi_conf *conf;
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 	struct fpga_manager *mgr;
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-	int ret;
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 	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
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 	if (!conf)
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@@ -154,31 +233,29 @@
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 	/* PROGRAM_B is active low */
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 	conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
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-	if (IS_ERR(conf->prog_b)) {
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-		dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
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-			PTR_ERR(conf->prog_b));
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-		return PTR_ERR(conf->prog_b);
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-	}
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+	if (IS_ERR(conf->prog_b))
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+		return dev_err_probe(&spi->dev, PTR_ERR(conf->prog_b),
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+				     "Failed to get PROGRAM_B gpio\n");
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+
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+	conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
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+	if (IS_ERR(conf->init_b))
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+		return dev_err_probe(&spi->dev, PTR_ERR(conf->init_b),
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+				     "Failed to get INIT_B gpio\n");
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 	conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
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-	if (IS_ERR(conf->done)) {
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-		dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
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-			PTR_ERR(conf->done));
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-		return PTR_ERR(conf->done);
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-	}
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+	if (IS_ERR(conf->done))
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+		return dev_err_probe(&spi->dev, PTR_ERR(conf->done),
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+				     "Failed to get DONE gpio\n");
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-	mgr = fpga_mgr_create(&spi->dev, "Xilinx Slave Serial FPGA Manager",
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-			      &xilinx_spi_ops, conf);
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+	mgr = devm_fpga_mgr_create(&spi->dev,
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+				   "Xilinx Slave Serial FPGA Manager",
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+				   &xilinx_spi_ops, conf);
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 	if (!mgr)
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 		return -ENOMEM;
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 	spi_set_drvdata(spi, mgr);
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-	ret = fpga_mgr_register(mgr);
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-	if (ret)
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-		fpga_mgr_free(mgr);
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-
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-	return ret;
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+	return fpga_mgr_register(mgr);
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 }
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 static int xilinx_spi_remove(struct spi_device *spi)