| .. | .. |
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| 157 | 157 | spi_message_init(&msg); |
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| 158 | 158 | tx[1].tx_buf = &refresh; |
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| 159 | 159 | tx[1].len = sizeof(refresh); |
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| 160 | | - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; |
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| 160 | + tx[1].delay.value = MACHXO2_REFRESH_USEC; |
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| 161 | + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; |
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| 161 | 162 | spi_message_add_tail(&tx[1], &msg); |
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| 162 | 163 | ret = spi_sync(spi, &msg); |
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| 163 | 164 | if (ret) |
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| .. | .. |
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| 208 | 209 | spi_message_init(&msg); |
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| 209 | 210 | tx[0].tx_buf = &enable; |
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| 210 | 211 | tx[0].len = sizeof(enable); |
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| 211 | | - tx[0].delay_usecs = MACHXO2_LOW_DELAY_USEC; |
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| 212 | + tx[0].delay.value = MACHXO2_LOW_DELAY_USEC; |
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| 213 | + tx[0].delay.unit = SPI_DELAY_UNIT_USECS; |
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| 212 | 214 | spi_message_add_tail(&tx[0], &msg); |
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| 213 | 215 | |
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| 214 | 216 | tx[1].tx_buf = &erase; |
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| .. | .. |
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| 271 | 273 | spi_message_init(&msg); |
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| 272 | 274 | tx.tx_buf = payload; |
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| 273 | 275 | tx.len = MACHXO2_BUF_SIZE; |
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| 274 | | - tx.delay_usecs = MACHXO2_HIGH_DELAY_USEC; |
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| 276 | + tx.delay.value = MACHXO2_HIGH_DELAY_USEC; |
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| 277 | + tx.delay.unit = SPI_DELAY_UNIT_USECS; |
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| 275 | 278 | spi_message_add_tail(&tx, &msg); |
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| 276 | 279 | ret = spi_sync(spi, &msg); |
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| 277 | 280 | if (ret) { |
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| .. | .. |
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| 320 | 323 | spi_message_init(&msg); |
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| 321 | 324 | tx[1].tx_buf = &refresh; |
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| 322 | 325 | tx[1].len = sizeof(refresh); |
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| 323 | | - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; |
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| 326 | + tx[1].delay.value = MACHXO2_REFRESH_USEC; |
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| 327 | + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; |
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| 324 | 328 | spi_message_add_tail(&tx[1], &msg); |
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| 325 | 329 | ret = spi_sync(spi, &msg); |
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| 326 | 330 | if (ret) |
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| .. | .. |
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| 360 | 364 | { |
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| 361 | 365 | struct device *dev = &spi->dev; |
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| 362 | 366 | struct fpga_manager *mgr; |
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| 363 | | - int ret; |
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| 364 | 367 | |
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| 365 | 368 | if (spi->max_speed_hz > MACHXO2_MAX_SPEED) { |
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| 366 | 369 | dev_err(dev, "Speed is too high\n"); |
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| 367 | 370 | return -EINVAL; |
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| 368 | 371 | } |
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| 369 | 372 | |
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| 370 | | - mgr = fpga_mgr_create(dev, "Lattice MachXO2 SPI FPGA Manager", |
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| 371 | | - &machxo2_ops, spi); |
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| 373 | + mgr = devm_fpga_mgr_create(dev, "Lattice MachXO2 SPI FPGA Manager", |
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| 374 | + &machxo2_ops, spi); |
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| 372 | 375 | if (!mgr) |
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| 373 | 376 | return -ENOMEM; |
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| 374 | 377 | |
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| 375 | 378 | spi_set_drvdata(spi, mgr); |
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| 376 | 379 | |
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| 377 | | - ret = fpga_mgr_register(mgr); |
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| 378 | | - if (ret) |
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| 379 | | - fpga_mgr_free(mgr); |
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| 380 | | - |
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| 381 | | - return ret; |
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| 380 | + return fpga_mgr_register(mgr); |
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| 382 | 381 | } |
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| 383 | 382 | |
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| 384 | 383 | static int machxo2_spi_remove(struct spi_device *spi) |
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