change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/fpga/Kconfig
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@@ -1,3 +1,4 @@
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+# SPDX-License-Identifier: GPL-2.0-only
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 #
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 # FPGA framework configuration
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 #
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@@ -25,9 +26,9 @@
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 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
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 config ALTERA_PR_IP_CORE
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-        tristate "Altera Partial Reconfiguration IP Core"
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-        help
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-          Core driver support for Altera Partial Reconfiguration IP component
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+	tristate "Altera Partial Reconfiguration IP Core"
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+	help
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+	  Core driver support for Altera Partial Reconfiguration IP component
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 config ALTERA_PR_IP_CORE_PLAT
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 	tristate "Platform support of Altera Partial Reconfiguration IP Core"
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@@ -45,17 +46,23 @@
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 	  using the passive serial interface over SPI.
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 config FPGA_MGR_ALTERA_CVP
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-	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
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+	tristate "Altera CvP FPGA Manager"
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 	depends on PCI
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 	help
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-	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
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-	  and Arria 10 Altera FPGAs using the CvP interface over PCIe.
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+	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
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+	  Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
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 config FPGA_MGR_ZYNQ_FPGA
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 	tristate "Xilinx Zynq FPGA"
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 	depends on ARCH_ZYNQ || COMPILE_TEST
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 	help
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 	  FPGA manager driver support for Xilinx Zynq FPGAs.
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+
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+config FPGA_MGR_STRATIX10_SOC
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+	tristate "Intel Stratix10 SoC FPGA Manager"
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+	depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
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+	help
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+	  FPGA manager driver support for the Intel Stratix10 SoC.
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 config FPGA_MGR_XILINX_SPI
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 	tristate "Xilinx Configuration over Slave Serial (SPI)"
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@@ -99,7 +106,7 @@
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 config ALTERA_FREEZE_BRIDGE
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 	tristate "Altera FPGA Freeze Bridge"
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-	depends on ARCH_SOCFPGA && FPGA_BRIDGE
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+	depends on FPGA_BRIDGE && HAS_IOMEM
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 	help
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 	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
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 	  freeze bridge is a bridge that exists in the FPGA fabric to
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@@ -135,6 +142,7 @@
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 	tristate "FPGA Device Feature List (DFL) support"
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 	select FPGA_BRIDGE
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 	select FPGA_REGION
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+	depends on HAS_IOMEM
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 	help
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 	  Device Feature List (DFL) defines a feature list structure that
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 	  creates a linked list of feature headers within the MMIO space
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@@ -149,7 +157,7 @@
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 config FPGA_DFL_FME
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 	tristate "FPGA DFL FME Driver"
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-	depends on FPGA_DFL
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+	depends on FPGA_DFL && HWMON && PERF_EVENTS
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 	help
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 	  The FPGA Management Engine (FME) is a feature device implemented
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 	  under Device Feature List (DFL) framework. Select this option to
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@@ -199,4 +207,13 @@
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 	  To compile this as a module, choose M here.
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+config FPGA_MGR_ZYNQMP_FPGA
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+	tristate "Xilinx ZynqMP FPGA"
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+	depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
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+	help
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+	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
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+	  This driver uses the processor configuration port(PCAP)
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+	  to configure the programmable logic(PL) through PS
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+	  on ZynqMP SoC.
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+
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 endif # FPGA