forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/dma/sprd-dma.c
....@@ -36,6 +36,8 @@
3636 #define SPRD_DMA_GLB_CHN_EN_STS		0x1c
3737 #define SPRD_DMA_GLB_DEBUG_STS		0x20
3838 #define SPRD_DMA_GLB_ARB_SEL_STS	0x24
39
+#define SPRD_DMA_GLB_2STAGE_GRP1	0x28
40
+#define SPRD_DMA_GLB_2STAGE_GRP2	0x2c
3941 #define SPRD_DMA_GLB_REQ_UID(uid)	(0x4 * ((uid) - 1))
4042 #define SPRD_DMA_GLB_REQ_UID_OFFSET	0x2000
4143 
....@@ -57,6 +59,20 @@
5759 #define SPRD_DMA_CHN_SRC_BLK_STEP	0x38
5860 #define SPRD_DMA_CHN_DES_BLK_STEP	0x3c
5961 
62
+/* SPRD_DMA_GLB_2STAGE_GRP register definition */
63
+#define SPRD_DMA_GLB_2STAGE_EN		BIT(24)
64
+#define SPRD_DMA_GLB_CHN_INT_MASK	GENMASK(23, 20)
65
+#define SPRD_DMA_GLB_DEST_INT		BIT(22)
66
+#define SPRD_DMA_GLB_SRC_INT		BIT(20)
67
+#define SPRD_DMA_GLB_LIST_DONE_TRG	BIT(19)
68
+#define SPRD_DMA_GLB_TRANS_DONE_TRG	BIT(18)
69
+#define SPRD_DMA_GLB_BLOCK_DONE_TRG	BIT(17)
70
+#define SPRD_DMA_GLB_FRAG_DONE_TRG	BIT(16)
71
+#define SPRD_DMA_GLB_TRG_OFFSET		16
72
+#define SPRD_DMA_GLB_DEST_CHN_MASK	GENMASK(13, 8)
73
+#define SPRD_DMA_GLB_DEST_CHN_OFFSET	8
74
+#define SPRD_DMA_GLB_SRC_CHN_MASK	GENMASK(5, 0)
75
+
6076 /* SPRD_DMA_CHN_INTC register definition */
6177 #define SPRD_DMA_INT_MASK		GENMASK(4, 0)
6278 #define SPRD_DMA_INT_CLR_OFFSET		24
....@@ -68,6 +84,7 @@
6884 
6985 /* SPRD_DMA_CHN_CFG register definition */
7086 #define SPRD_DMA_CHN_EN			BIT(0)
87
+#define SPRD_DMA_LINKLIST_EN		BIT(4)
7188 #define SPRD_DMA_WAIT_BDONE_OFFSET	24
7289 #define SPRD_DMA_DONOT_WAIT_BDONE	1
7390 
....@@ -82,6 +99,7 @@
8299 /* DMA_CHN_WARP_* register definition */
83100 #define SPRD_DMA_HIGH_ADDR_MASK		GENMASK(31, 28)
84101 #define SPRD_DMA_LOW_ADDR_MASK		GENMASK(31, 0)
102
+#define SPRD_DMA_WRAP_ADDR_MASK		GENMASK(27, 0)
85103 #define SPRD_DMA_HIGH_ADDR_OFFSET	4
86104 
87105 /* SPRD_DMA_CHN_INTC register definition */
....@@ -101,9 +119,11 @@
101119 #define SPRD_DMA_SWT_MODE_OFFSET	26
102120 #define SPRD_DMA_REQ_MODE_OFFSET	24
103121 #define SPRD_DMA_REQ_MODE_MASK		GENMASK(1, 0)
122
+#define SPRD_DMA_WRAP_SEL_DEST		BIT(23)
123
+#define SPRD_DMA_WRAP_EN		BIT(22)
104124 #define SPRD_DMA_FIX_SEL_OFFSET		21
105125 #define SPRD_DMA_FIX_EN_OFFSET		20
106
-#define SPRD_DMA_LLIST_END_OFFSET	19
126
+#define SPRD_DMA_LLIST_END		BIT(19)
107127 #define SPRD_DMA_FRG_LEN_MASK		GENMASK(16, 0)
108128 
109129 /* SPRD_DMA_CHN_BLK_LEN register definition */
....@@ -116,6 +136,15 @@
116136 #define SPRD_DMA_DEST_TRSF_STEP_OFFSET	16
117137 #define SPRD_DMA_SRC_TRSF_STEP_OFFSET	0
118138 #define SPRD_DMA_TRSF_STEP_MASK		GENMASK(15, 0)
139
+
140
+/* SPRD DMA_SRC_BLK_STEP register definition */
141
+#define SPRD_DMA_LLIST_HIGH_MASK	GENMASK(31, 28)
142
+#define SPRD_DMA_LLIST_HIGH_SHIFT	28
143
+
144
+/* define DMA channel mode & trigger mode mask */
145
+#define SPRD_DMA_CHN_MODE_MASK		GENMASK(7, 0)
146
+#define SPRD_DMA_TRG_MODE_MASK		GENMASK(7, 0)
147
+#define SPRD_DMA_INT_TYPE_MASK		GENMASK(7, 0)
119148 
120149 /* define the DMA transfer step type */
121150 #define SPRD_DMA_NONE_STEP		0
....@@ -158,15 +187,20 @@
158187 struct sprd_dma_desc {
159188 	struct virt_dma_desc	vd;
160189 	struct sprd_dma_chn_hw	chn_hw;
190
+	enum dma_transfer_direction dir;
161191 };
162192 
163193 /* dma channel description */
164194 struct sprd_dma_chn {
165195 	struct virt_dma_chan	vc;
166196 	void __iomem		*chn_base;
197
+	struct sprd_dma_linklist	linklist;
167198 	struct dma_slave_config	slave_cfg;
168199 	u32			chn_num;
169200 	u32			dev_id;
201
+	enum sprd_dma_chn_mode	chn_mode;
202
+	enum sprd_dma_trg_mode	trg_mode;
203
+	enum sprd_dma_int_type	int_type;
170204 	struct sprd_dma_desc	*cur_desc;
171205 };
172206 
....@@ -178,7 +212,7 @@
178212 	struct clk		*ashb_clk;
179213 	int			irq;
180214 	u32			total_chns;
181
-	struct sprd_dma_chn	channels[0];
215
+	struct sprd_dma_chn	channels[];
182216 };
183217 
184218 static void sprd_dma_free_desc(struct virt_dma_desc *vd);
....@@ -202,6 +236,16 @@
202236 static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd)
203237 {
204238 	return container_of(vd, struct sprd_dma_desc, vd);
239
+}
240
+
241
+static void sprd_dma_glb_update(struct sprd_dma_dev *sdev, u32 reg,
242
+				u32 mask, u32 val)
243
+{
244
+	u32 orig = readl(sdev->glb_base + reg);
245
+	u32 tmp;
246
+
247
+	tmp = (orig & ~mask) | val;
248
+	writel(tmp, sdev->glb_base + reg);
205249 }
206250 
207251 static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg,
....@@ -330,6 +374,17 @@
330374 	sprd_dma_disable_chn(schan);
331375 }
332376 
377
+static unsigned long sprd_dma_get_src_addr(struct sprd_dma_chn *schan)
378
+{
379
+	unsigned long addr, addr_high;
380
+
381
+	addr = readl(schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
382
+	addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_PTR) &
383
+		    SPRD_DMA_HIGH_ADDR_MASK;
384
+
385
+	return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
386
+}
387
+
333388 static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan)
334389 {
335390 	unsigned long addr, addr_high;
....@@ -376,6 +431,83 @@
376431 	return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK;
377432 }
378433 
434
+static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
435
+{
436
+	struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
437
+	u32 val, chn = schan->chn_num + 1;
438
+
439
+	switch (schan->chn_mode) {
440
+	case SPRD_DMA_SRC_CHN0:
441
+		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
442
+		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
443
+		val |= SPRD_DMA_GLB_2STAGE_EN;
444
+		if (schan->int_type != SPRD_DMA_NO_INT)
445
+			val |= SPRD_DMA_GLB_SRC_INT;
446
+
447
+		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
448
+		break;
449
+
450
+	case SPRD_DMA_SRC_CHN1:
451
+		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
452
+		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
453
+		val |= SPRD_DMA_GLB_2STAGE_EN;
454
+		if (schan->int_type != SPRD_DMA_NO_INT)
455
+			val |= SPRD_DMA_GLB_SRC_INT;
456
+
457
+		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
458
+		break;
459
+
460
+	case SPRD_DMA_DST_CHN0:
461
+		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
462
+			SPRD_DMA_GLB_DEST_CHN_MASK;
463
+		val |= SPRD_DMA_GLB_2STAGE_EN;
464
+		if (schan->int_type != SPRD_DMA_NO_INT)
465
+			val |= SPRD_DMA_GLB_DEST_INT;
466
+
467
+		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
468
+		break;
469
+
470
+	case SPRD_DMA_DST_CHN1:
471
+		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
472
+			SPRD_DMA_GLB_DEST_CHN_MASK;
473
+		val |= SPRD_DMA_GLB_2STAGE_EN;
474
+		if (schan->int_type != SPRD_DMA_NO_INT)
475
+			val |= SPRD_DMA_GLB_DEST_INT;
476
+
477
+		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
478
+		break;
479
+
480
+	default:
481
+		dev_err(sdev->dma_dev.dev, "invalid channel mode setting %d\n",
482
+			schan->chn_mode);
483
+		return -EINVAL;
484
+	}
485
+
486
+	return 0;
487
+}
488
+
489
+static void sprd_dma_set_pending(struct sprd_dma_chn *schan, bool enable)
490
+{
491
+	struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
492
+	u32 reg, val, req_id;
493
+
494
+	if (schan->dev_id == SPRD_DMA_SOFTWARE_UID)
495
+		return;
496
+
497
+	/* The DMA request id always starts from 0. */
498
+	req_id = schan->dev_id - 1;
499
+
500
+	if (req_id < 32) {
501
+		reg = SPRD_DMA_GLB_REQ_PEND0_EN;
502
+		val = BIT(req_id);
503
+	} else {
504
+		reg = SPRD_DMA_GLB_REQ_PEND1_EN;
505
+		val = BIT(req_id - 32);
506
+	}
507
+
508
+	sprd_dma_glb_update(sdev, reg, val, enable ? val : 0);
509
+}
510
+
379511 static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan,
380512 				    struct sprd_dma_desc *sdesc)
381513 {
....@@ -410,22 +542,34 @@
410542 	schan->cur_desc = to_sprd_dma_desc(vd);
411543 
412544 	/*
545
+	 * Set 2-stage configuration if the channel starts one 2-stage
546
+	 * transfer.
547
+	 */
548
+	if (schan->chn_mode && sprd_dma_set_2stage_config(schan))
549
+		return;
550
+
551
+	/*
413552 	 * Copy the DMA configuration from DMA descriptor to this hardware
414553 	 * channel.
415554 	 */
416555 	sprd_dma_set_chn_config(schan, schan->cur_desc);
417556 	sprd_dma_set_uid(schan);
557
+	sprd_dma_set_pending(schan, true);
418558 	sprd_dma_enable_chn(schan);
419559 
420
-	if (schan->dev_id == SPRD_DMA_SOFTWARE_UID)
560
+	if (schan->dev_id == SPRD_DMA_SOFTWARE_UID &&
561
+	    schan->chn_mode != SPRD_DMA_DST_CHN0 &&
562
+	    schan->chn_mode != SPRD_DMA_DST_CHN1)
421563 		sprd_dma_soft_request(schan);
422564 }
423565 
424566 static void sprd_dma_stop(struct sprd_dma_chn *schan)
425567 {
426568 	sprd_dma_stop_and_disable(schan);
569
+	sprd_dma_set_pending(schan, false);
427570 	sprd_dma_unset_uid(schan);
428571 	sprd_dma_clear_int(schan);
572
+	schan->cur_desc = NULL;
429573 }
430574 
431575 static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc,
....@@ -449,7 +593,7 @@
449593 	struct sprd_dma_desc *sdesc;
450594 	enum sprd_dma_req_mode req_type;
451595 	enum sprd_dma_int_type int_type;
452
-	bool trans_done = false;
596
+	bool trans_done = false, cyclic = false;
453597 	u32 i;
454598 
455599 	while (irq_status) {
....@@ -458,19 +602,30 @@
458602 		schan = &sdev->channels[i];
459603 
460604 		spin_lock(&schan->vc.lock);
605
+
606
+		sdesc = schan->cur_desc;
607
+		if (!sdesc) {
608
+			spin_unlock(&schan->vc.lock);
609
+			return IRQ_HANDLED;
610
+		}
611
+
461612 		int_type = sprd_dma_get_int_type(schan);
462613 		req_type = sprd_dma_get_req_type(schan);
463614 		sprd_dma_clear_int(schan);
464615 
465
-		sdesc = schan->cur_desc;
466
-
467
-		/* Check if the dma request descriptor is done. */
468
-		trans_done = sprd_dma_check_trans_done(sdesc, int_type,
469
-						       req_type);
470
-		if (trans_done == true) {
471
-			vchan_cookie_complete(&sdesc->vd);
472
-			schan->cur_desc = NULL;
473
-			sprd_dma_start(schan);
616
+		/* cyclic mode schedule callback */
617
+		cyclic = schan->linklist.phy_addr ? true : false;
618
+		if (cyclic == true) {
619
+			vchan_cyclic_callback(&sdesc->vd);
620
+		} else {
621
+			/* Check if the dma request descriptor is done. */
622
+			trans_done = sprd_dma_check_trans_done(sdesc, int_type,
623
+							       req_type);
624
+			if (trans_done == true) {
625
+				vchan_cookie_complete(&sdesc->vd);
626
+				schan->cur_desc = NULL;
627
+				sprd_dma_start(schan);
628
+			}
474629 		}
475630 		spin_unlock(&schan->vc.lock);
476631 	}
....@@ -480,15 +635,7 @@
480635 
481636 static int sprd_dma_alloc_chan_resources(struct dma_chan *chan)
482637 {
483
-	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
484
-	int ret;
485
-
486
-	ret = pm_runtime_get_sync(chan->device->dev);
487
-	if (ret < 0)
488
-		return ret;
489
-
490
-	schan->dev_id = SPRD_DMA_SOFTWARE_UID;
491
-	return 0;
638
+	return pm_runtime_get_sync(chan->device->dev);
492639 }
493640 
494641 static void sprd_dma_free_chan_resources(struct dma_chan *chan)
....@@ -540,7 +687,12 @@
540687 		else
541688 			pos = 0;
542689 	} else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
543
-		pos = sprd_dma_get_dst_addr(schan);
690
+		struct sprd_dma_desc *sdesc = schan->cur_desc;
691
+
692
+		if (sdesc->dir == DMA_DEV_TO_MEM)
693
+			pos = sprd_dma_get_dst_addr(schan);
694
+		else
695
+			pos = sprd_dma_get_src_addr(schan);
544696 	} else {
545697 		pos = 0;
546698 	}
....@@ -590,7 +742,8 @@
590742 }
591743 
592744 static int sprd_dma_fill_desc(struct dma_chan *chan,
593
-			      struct sprd_dma_desc *sdesc,
745
+			      struct sprd_dma_chn_hw *hw,
746
+			      unsigned int sglen, int sg_index,
594747 			      dma_addr_t src, dma_addr_t dst, u32 len,
595748 			      enum dma_transfer_direction dir,
596749 			      unsigned long flags,
....@@ -598,11 +751,12 @@
598751 {
599752 	struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
600753 	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
601
-	struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
754
+	enum sprd_dma_chn_mode chn_mode = schan->chn_mode;
602755 	u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK;
603756 	u32 int_mode = flags & SPRD_DMA_INT_MASK;
604757 	int src_datawidth, dst_datawidth, src_step, dst_step;
605758 	u32 temp, fix_mode = 0, fix_en = 0;
759
+	phys_addr_t llist_ptr;
606760 
607761 	if (dir == DMA_MEM_TO_DEV) {
608762 		src_step = sprd_dma_get_step(slave_cfg->src_addr_width);
....@@ -610,7 +764,16 @@
610764 			dev_err(sdev->dma_dev.dev, "invalid source step\n");
611765 			return src_step;
612766 		}
613
-		dst_step = SPRD_DMA_NONE_STEP;
767
+
768
+		/*
769
+		 * For 2-stage transfer, destination channel step can not be 0,
770
+		 * since destination device is AON IRAM.
771
+		 */
772
+		if (chn_mode == SPRD_DMA_DST_CHN0 ||
773
+		    chn_mode == SPRD_DMA_DST_CHN1)
774
+			dst_step = src_step;
775
+		else
776
+			dst_step = SPRD_DMA_NONE_STEP;
614777 	} else {
615778 		dst_step = sprd_dma_get_step(slave_cfg->dst_addr_width);
616779 		if (dst_step < 0) {
....@@ -668,6 +831,8 @@
668831 	temp |= req_mode << SPRD_DMA_REQ_MODE_OFFSET;
669832 	temp |= fix_mode << SPRD_DMA_FIX_SEL_OFFSET;
670833 	temp |= fix_en << SPRD_DMA_FIX_EN_OFFSET;
834
+	temp |= schan->linklist.wrap_addr ?
835
+		SPRD_DMA_WRAP_EN | SPRD_DMA_WRAP_SEL_DEST : 0;
671836 	temp |= slave_cfg->src_maxburst & SPRD_DMA_FRG_LEN_MASK;
672837 	hw->frg_len = temp;
673838 
....@@ -678,10 +843,57 @@
678843 	temp |= (src_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
679844 	hw->trsf_step = temp;
680845 
846
+	/* link-list configuration */
847
+	if (schan->linklist.phy_addr) {
848
+		hw->cfg |= SPRD_DMA_LINKLIST_EN;
849
+
850
+		/* link-list index */
851
+		temp = sglen ? (sg_index + 1) % sglen : 0;
852
+
853
+		/* Next link-list configuration's physical address offset */
854
+		temp = temp * sizeof(*hw) + SPRD_DMA_CHN_SRC_ADDR;
855
+		/*
856
+		 * Set the link-list pointer point to next link-list
857
+		 * configuration's physical address.
858
+		 */
859
+		llist_ptr = schan->linklist.phy_addr + temp;
860
+		hw->llist_ptr = lower_32_bits(llist_ptr);
861
+		hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) &
862
+			SPRD_DMA_LLIST_HIGH_MASK;
863
+
864
+		if (schan->linklist.wrap_addr) {
865
+			hw->wrap_ptr |= schan->linklist.wrap_addr &
866
+				SPRD_DMA_WRAP_ADDR_MASK;
867
+			hw->wrap_to |= dst & SPRD_DMA_WRAP_ADDR_MASK;
868
+		}
869
+	} else {
870
+		hw->llist_ptr = 0;
871
+		hw->src_blk_step = 0;
872
+	}
873
+
681874 	hw->frg_step = 0;
682
-	hw->src_blk_step = 0;
683875 	hw->des_blk_step = 0;
684876 	return 0;
877
+}
878
+
879
+static int sprd_dma_fill_linklist_desc(struct dma_chan *chan,
880
+				       unsigned int sglen, int sg_index,
881
+				       dma_addr_t src, dma_addr_t dst, u32 len,
882
+				       enum dma_transfer_direction dir,
883
+				       unsigned long flags,
884
+				       struct dma_slave_config *slave_cfg)
885
+{
886
+	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
887
+	struct sprd_dma_chn_hw *hw;
888
+
889
+	if (!schan->linklist.virt_addr)
890
+		return -EINVAL;
891
+
892
+	hw = (struct sprd_dma_chn_hw *)(schan->linklist.virt_addr +
893
+					sg_index * sizeof(*hw));
894
+
895
+	return sprd_dma_fill_desc(chan, hw, sglen, sg_index, src, dst, len,
896
+				  dir, flags, slave_cfg);
685897 }
686898 
687899 static struct dma_async_tx_descriptor *
....@@ -747,18 +959,43 @@
747959 	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
748960 	struct dma_slave_config *slave_cfg = &schan->slave_cfg;
749961 	dma_addr_t src = 0, dst = 0;
962
+	dma_addr_t start_src = 0, start_dst = 0;
750963 	struct sprd_dma_desc *sdesc;
751964 	struct scatterlist *sg;
752965 	u32 len = 0;
753966 	int ret, i;
754967 
755
-	/* TODO: now we only support one sg for each DMA configuration. */
756
-	if (!is_slave_direction(dir) || sglen > 1)
968
+	if (!is_slave_direction(dir))
757969 		return NULL;
970
+
971
+	if (context) {
972
+		struct sprd_dma_linklist *ll_cfg =
973
+			(struct sprd_dma_linklist *)context;
974
+
975
+		schan->linklist.phy_addr = ll_cfg->phy_addr;
976
+		schan->linklist.virt_addr = ll_cfg->virt_addr;
977
+		schan->linklist.wrap_addr = ll_cfg->wrap_addr;
978
+	} else {
979
+		schan->linklist.phy_addr = 0;
980
+		schan->linklist.virt_addr = 0;
981
+		schan->linklist.wrap_addr = 0;
982
+	}
983
+
984
+	/*
985
+	 * Set channel mode, interrupt mode and trigger mode for 2-stage
986
+	 * transfer.
987
+	 */
988
+	schan->chn_mode =
989
+		(flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
990
+	schan->trg_mode =
991
+		(flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
992
+	schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK;
758993 
759994 	sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
760995 	if (!sdesc)
761996 		return NULL;
997
+
998
+	sdesc->dir = dir;
762999 
7631000 	for_each_sg(sgl, sg, sglen, i) {
7641001 		len = sg_dma_len(sg);
....@@ -770,10 +1007,30 @@
7701007 			src = slave_cfg->src_addr;
7711008 			dst = sg_dma_address(sg);
7721009 		}
1010
+
1011
+		if (!i) {
1012
+			start_src = src;
1013
+			start_dst = dst;
1014
+		}
1015
+
1016
+		/*
1017
+		 * The link-list mode needs at least 2 link-list
1018
+		 * configurations. If there is only one sg, it doesn't
1019
+		 * need to fill the link-list configuration.
1020
+		 */
1021
+		if (sglen < 2)
1022
+			break;
1023
+
1024
+		ret = sprd_dma_fill_linklist_desc(chan, sglen, i, src, dst, len,
1025
+						  dir, flags, slave_cfg);
1026
+		if (ret) {
1027
+			kfree(sdesc);
1028
+			return NULL;
1029
+		}
7731030 	}
7741031 
775
-	ret = sprd_dma_fill_desc(chan, sdesc, src, dst, len, dir, flags,
776
-				 slave_cfg);
1032
+	ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, start_src,
1033
+				 start_dst, len, dir, flags, slave_cfg);
7771034 	if (ret) {
7781035 		kfree(sdesc);
7791036 		return NULL;
....@@ -787,9 +1044,6 @@
7871044 {
7881045 	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
7891046 	struct dma_slave_config *slave_cfg = &schan->slave_cfg;
790
-
791
-	if (!is_slave_direction(config->direction))
792
-		return -EINVAL;
7931047 
7941048 	memcpy(slave_cfg, config, sizeof(*config));
7951049 	return 0;
....@@ -852,13 +1106,10 @@
8521106 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param)
8531107 {
8541108 	struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
855
-	struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
856
-	u32 req = *(u32 *)param;
1109
+	u32 slave_id = *(u32 *)param;
8571110 
858
-	if (req < sdev->total_chns)
859
-		return req == schan->chn_num + 1;
860
-	else
861
-		return false;
1111
+	schan->dev_id = slave_id;
1112
+	return true;
8621113 }
8631114 
8641115 static int sprd_dma_probe(struct platform_device *pdev)
....@@ -866,7 +1117,6 @@
8661117 	struct device_node *np = pdev->dev.of_node;
8671118 	struct sprd_dma_dev *sdev;
8681119 	struct sprd_dma_chn *dma_chn;
869
-	struct resource *res;
8701120 	u32 chn_count;
8711121 	int ret, i;
8721122 
....@@ -912,8 +1162,7 @@
9121162 		dev_warn(&pdev->dev, "no interrupts for the dma controller\n");
9131163 	}
9141164 
915
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
916
-	sdev->glb_base = devm_ioremap_resource(&pdev->dev, res);
1165
+	sdev->glb_base = devm_platform_ioremap_resource(pdev, 0);
9171166 	if (IS_ERR(sdev->glb_base))
9181167 		return PTR_ERR(sdev->glb_base);
9191168 
....@@ -987,11 +1236,8 @@
9871236 {
9881237 	struct sprd_dma_dev *sdev = platform_get_drvdata(pdev);
9891238 	struct sprd_dma_chn *c, *cn;
990
-	int ret;
9911239 
992
-	ret = pm_runtime_get_sync(&pdev->dev);
993
-	if (ret < 0)
994
-		return ret;
1240
+	pm_runtime_get_sync(&pdev->dev);
9951241 
9961242 	/* explicitly free the irq */
9971243 	if (sdev->irq > 0)
....@@ -1058,4 +1304,5 @@
10581304 MODULE_LICENSE("GPL v2");
10591305 MODULE_DESCRIPTION("DMA driver for Spreadtrum");
10601306 MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
1307
+MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
10611308 MODULE_ALIAS("platform:sprd-dma");