change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/dma/k3dma.c
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@@ -1,10 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2013 - 2015 Linaro Ltd.
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  * Copyright (c) 2013 Hisilicon Limited.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/sched.h>
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 #include <linux/device.h>
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@@ -52,8 +49,6 @@
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 #define CX_SRC			0x814
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 #define CX_DST			0x818
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 #define CX_CFG			0x81c
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-#define AXI_CFG			0x820
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-#define AXI_CFG_DEFAULT		0x201201
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 #define CX_LLI_CHAIN_EN		0x2
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 #define CX_CFG_EN		0x1
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@@ -87,10 +82,10 @@
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 	struct virt_dma_chan	vc;
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 	struct k3_dma_phy	*phy;
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 	struct list_head	node;
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-	enum dma_transfer_direction dir;
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 	dma_addr_t		dev_addr;
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 	enum dma_status		status;
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 	bool			cyclic;
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+	struct dma_slave_config	slave_config;
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 };
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 struct k3_dma_phy {
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@@ -113,10 +108,23 @@
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 	struct dma_pool		*pool;
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 	u32			dma_channels;
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 	u32			dma_requests;
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+	u32			dma_channel_mask;
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 	unsigned int		irq;
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 };
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+
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+#define K3_FLAG_NOCLK	BIT(1)
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+
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+struct k3dma_soc_data {
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+	unsigned long flags;
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+};
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+
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+
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 #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
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+
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+static int k3_dma_config_write(struct dma_chan *chan,
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+			       enum dma_transfer_direction dir,
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+			       struct dma_slave_config *cfg);
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 static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
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 {
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@@ -157,7 +165,6 @@
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 	writel_relaxed(hw->count, phy->base + CX_CNT0);
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 	writel_relaxed(hw->saddr, phy->base + CX_SRC);
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 	writel_relaxed(hw->daddr, phy->base + CX_DST);
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-	writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
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 	writel_relaxed(hw->config, phy->base + CX_CFG);
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 }
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@@ -290,9 +297,9 @@
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 	return -EAGAIN;
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 }
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-static void k3_dma_tasklet(unsigned long arg)
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+static void k3_dma_tasklet(struct tasklet_struct *t)
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 {
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-	struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
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+	struct k3_dma_dev *d = from_tasklet(d, t, task);
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 	struct k3_dma_phy *p;
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 	struct k3_dma_chan *c, *cn;
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 	unsigned pch, pch_alloc = 0;
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@@ -316,6 +323,9 @@
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 	/* check new channel request in d->chan_pending */
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 	spin_lock_irq(&d->lock);
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 	for (pch = 0; pch < d->dma_channels; pch++) {
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+		if (!(d->dma_channel_mask & (1 << pch)))
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+			continue;
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+
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 		p = &d->phy[pch];
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 		if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
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@@ -333,6 +343,9 @@
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 	spin_unlock_irq(&d->lock);
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 	for (pch = 0; pch < d->dma_channels; pch++) {
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+		if (!(d->dma_channel_mask & (1 << pch)))
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+			continue;
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+
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 		if (pch_alloc & (1 << pch)) {
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 			p = &d->phy[pch];
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 			c = p->vchan;
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@@ -507,14 +520,8 @@
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 		copy = min_t(size_t, len, DMA_MAX_SIZE);
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 		k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
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-		if (c->dir == DMA_MEM_TO_DEV) {
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-			src += copy;
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-		} else if (c->dir == DMA_DEV_TO_MEM) {
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-			dst += copy;
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-		} else {
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-			src += copy;
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-			dst += copy;
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-		}
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+		src += copy;
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+		dst += copy;
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 		len -= copy;
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 	} while (len);
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@@ -548,6 +555,7 @@
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 	if (!ds)
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 		return NULL;
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 	num = 0;
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+	k3_dma_config_write(chan, dir, &c->slave_config);
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 	for_each_sg(sgl, sg, sglen, i) {
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 		addr = sg_dma_address(sg);
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@@ -608,6 +616,7 @@
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 	avail = buf_len;
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 	total = avail;
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 	num = 0;
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+	k3_dma_config_write(chan, dir, &c->slave_config);
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 	if (period_len < modulo)
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 		modulo = period_len;
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@@ -648,18 +657,26 @@
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 			 struct dma_slave_config *cfg)
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 {
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 	struct k3_dma_chan *c = to_k3_chan(chan);
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+
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+	memcpy(&c->slave_config, cfg, sizeof(*cfg));
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+
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+	return 0;
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+}
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+
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+static int k3_dma_config_write(struct dma_chan *chan,
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+			       enum dma_transfer_direction dir,
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+			       struct dma_slave_config *cfg)
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+{
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+	struct k3_dma_chan *c = to_k3_chan(chan);
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 	u32 maxburst = 0, val = 0;
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 	enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
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-	if (cfg == NULL)
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-		return -EINVAL;
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-	c->dir = cfg->direction;
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-	if (c->dir == DMA_DEV_TO_MEM) {
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+	if (dir == DMA_DEV_TO_MEM) {
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 		c->ccfg = CX_CFG_DSTINCR;
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 		c->dev_addr = cfg->src_addr;
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 		maxburst = cfg->src_maxburst;
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 		width = cfg->src_addr_width;
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-	} else if (c->dir == DMA_MEM_TO_DEV) {
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+	} else if (dir == DMA_MEM_TO_DEV) {
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 		c->ccfg = CX_CFG_SRCINCR;
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 		c->dev_addr = cfg->dst_addr;
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 		maxburst = cfg->dst_maxburst;
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@@ -788,8 +805,21 @@
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 	return 0;
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 }
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+static const struct k3dma_soc_data k3_v1_dma_data = {
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+	.flags = 0,
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+};
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+
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+static const struct k3dma_soc_data asp_v1_dma_data = {
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+	.flags = K3_FLAG_NOCLK,
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+};
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+
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 static const struct of_device_id k3_pdma_dt_ids[] = {
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-	{ .compatible = "hisilicon,k3-dma-1.0", },
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+	{ .compatible = "hisilicon,k3-dma-1.0",
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+	  .data = &k3_v1_dma_data
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+	},
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+	{ .compatible = "hisilicon,hisi-pcm-asp-dma-1.0",
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+	  .data = &asp_v1_dma_data
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+	},
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 	{}
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 };
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 MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
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@@ -808,20 +838,20 @@
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 static int k3_dma_probe(struct platform_device *op)
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 {
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+	const struct k3dma_soc_data *soc_data;
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 	struct k3_dma_dev *d;
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 	const struct of_device_id *of_id;
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-	struct resource *iores;
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 	int i, ret, irq = 0;
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-
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-	iores = platform_get_resource(op, IORESOURCE_MEM, 0);
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-	if (!iores)
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-		return -EINVAL;
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 	d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
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 	if (!d)
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 		return -ENOMEM;
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-	d->base = devm_ioremap_resource(&op->dev, iores);
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+	soc_data = device_get_match_data(&op->dev);
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+	if (!soc_data)
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+		return -EINVAL;
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+
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+	d->base = devm_platform_ioremap_resource(op, 0);
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 	if (IS_ERR(d->base))
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 		return PTR_ERR(d->base);
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@@ -831,12 +861,21 @@
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 				"dma-channels", &d->dma_channels);
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 		of_property_read_u32((&op->dev)->of_node,
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 				"dma-requests", &d->dma_requests);
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+		ret = of_property_read_u32((&op->dev)->of_node,
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+				"dma-channel-mask", &d->dma_channel_mask);
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+		if (ret) {
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+			dev_warn(&op->dev,
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+				 "dma-channel-mask doesn't exist, considering all as available.\n");
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+			d->dma_channel_mask = (u32)~0UL;
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+		}
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 	}
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-	d->clk = devm_clk_get(&op->dev, NULL);
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-	if (IS_ERR(d->clk)) {
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-		dev_err(&op->dev, "no dma clk\n");
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-		return PTR_ERR(d->clk);
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+	if (!(soc_data->flags & K3_FLAG_NOCLK)) {
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+		d->clk = devm_clk_get(&op->dev, NULL);
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+		if (IS_ERR(d->clk)) {
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+			dev_err(&op->dev, "no dma clk\n");
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+			return PTR_ERR(d->clk);
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+		}
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 	}
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 	irq = platform_get_irq(op, 0);
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@@ -860,8 +899,12 @@
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 		return -ENOMEM;
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 	for (i = 0; i < d->dma_channels; i++) {
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-		struct k3_dma_phy *p = &d->phy[i];
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+		struct k3_dma_phy *p;
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+		if (!(d->dma_channel_mask & BIT(i)))
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+			continue;
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+
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+		p = &d->phy[i];
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 		p->idx = i;
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 		p->base = d->base + i * 0x40;
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 	}
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@@ -919,7 +962,7 @@
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 	spin_lock_init(&d->lock);
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 	INIT_LIST_HEAD(&d->chan_pending);
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-	tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
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+	tasklet_setup(&d->task, k3_dma_tasklet);
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 	platform_set_drvdata(op, d);
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 	dev_info(&op->dev, "initialized\n");
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