| .. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
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| 3 | 4 | * |
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| 4 | 5 | * Author: |
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| 5 | 6 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 |
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| 6 | 7 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 |
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| 7 | | - * |
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| 8 | | - * This is free software; you can redistribute it and/or modify |
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| 9 | | - * it under the terms of the GNU General Public License as published by |
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| 10 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 11 | | - * (at your option) any later version. |
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| 12 | | - * |
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| 13 | 8 | */ |
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| 14 | 9 | #ifndef __DMA_FSLDMA_H |
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| 15 | 10 | #define __DMA_FSLDMA_H |
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| .. | .. |
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| 196 | 191 | #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) |
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| 197 | 192 | #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) |
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| 198 | 193 | |
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| 199 | | -#ifndef __powerpc64__ |
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| 200 | | -static u64 in_be64(const u64 __iomem *addr) |
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| 194 | +#ifdef CONFIG_PPC |
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| 195 | +#define fsl_ioread32(p) in_le32(p) |
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| 196 | +#define fsl_ioread32be(p) in_be32(p) |
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| 197 | +#define fsl_iowrite32(v, p) out_le32(p, v) |
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| 198 | +#define fsl_iowrite32be(v, p) out_be32(p, v) |
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| 199 | + |
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| 200 | +#ifdef __powerpc64__ |
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| 201 | +#define fsl_ioread64(p) in_le64(p) |
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| 202 | +#define fsl_ioread64be(p) in_be64(p) |
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| 203 | +#define fsl_iowrite64(v, p) out_le64(p, v) |
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| 204 | +#define fsl_iowrite64be(v, p) out_be64(p, v) |
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| 205 | +#else |
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| 206 | +static u64 fsl_ioread64(const u64 __iomem *addr) |
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| 201 | 207 | { |
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| 202 | | - return ((u64)in_be32((u32 __iomem *)addr) << 32) | |
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| 203 | | - (in_be32((u32 __iomem *)addr + 1)); |
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| 208 | + u32 val_lo = in_le32((u32 __iomem *)addr); |
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| 209 | + u32 val_hi = in_le32((u32 __iomem *)addr + 1); |
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| 210 | + |
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| 211 | + return ((u64)val_hi << 32) + val_lo; |
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| 204 | 212 | } |
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| 205 | 213 | |
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| 206 | | -static void out_be64(u64 __iomem *addr, u64 val) |
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| 207 | | -{ |
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| 208 | | - out_be32((u32 __iomem *)addr, val >> 32); |
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| 209 | | - out_be32((u32 __iomem *)addr + 1, (u32)val); |
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| 210 | | -} |
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| 211 | | - |
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| 212 | | -/* There is no asm instructions for 64 bits reverse loads and stores */ |
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| 213 | | -static u64 in_le64(const u64 __iomem *addr) |
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| 214 | | -{ |
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| 215 | | - return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) | |
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| 216 | | - (in_le32((u32 __iomem *)addr)); |
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| 217 | | -} |
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| 218 | | - |
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| 219 | | -static void out_le64(u64 __iomem *addr, u64 val) |
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| 214 | +static void fsl_iowrite64(u64 val, u64 __iomem *addr) |
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| 220 | 215 | { |
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| 221 | 216 | out_le32((u32 __iomem *)addr + 1, val >> 32); |
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| 222 | 217 | out_le32((u32 __iomem *)addr, (u32)val); |
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| 223 | 218 | } |
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| 219 | + |
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| 220 | +static u64 fsl_ioread64be(const u64 __iomem *addr) |
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| 221 | +{ |
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| 222 | + u32 val_hi = in_be32((u32 __iomem *)addr); |
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| 223 | + u32 val_lo = in_be32((u32 __iomem *)addr + 1); |
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| 224 | + |
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| 225 | + return ((u64)val_hi << 32) + val_lo; |
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| 226 | +} |
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| 227 | + |
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| 228 | +static void fsl_iowrite64be(u64 val, u64 __iomem *addr) |
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| 229 | +{ |
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| 230 | + out_be32((u32 __iomem *)addr, val >> 32); |
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| 231 | + out_be32((u32 __iomem *)addr + 1, (u32)val); |
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| 232 | +} |
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| 233 | +#endif |
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| 224 | 234 | #endif |
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| 225 | 235 | |
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| 226 | | -#define DMA_IN(fsl_chan, addr, width) \ |
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| 227 | | - (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ |
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| 228 | | - in_be##width(addr) : in_le##width(addr)) |
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| 229 | | -#define DMA_OUT(fsl_chan, addr, val, width) \ |
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| 230 | | - (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ |
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| 231 | | - out_be##width(addr, val) : out_le##width(addr, val)) |
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| 236 | +#if defined(CONFIG_ARM64) || defined(CONFIG_ARM) |
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| 237 | +#define fsl_ioread32(p) ioread32(p) |
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| 238 | +#define fsl_ioread32be(p) ioread32be(p) |
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| 239 | +#define fsl_iowrite32(v, p) iowrite32(v, p) |
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| 240 | +#define fsl_iowrite32be(v, p) iowrite32be(v, p) |
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| 241 | +#define fsl_ioread64(p) ioread64(p) |
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| 242 | +#define fsl_ioread64be(p) ioread64be(p) |
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| 243 | +#define fsl_iowrite64(v, p) iowrite64(v, p) |
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| 244 | +#define fsl_iowrite64be(v, p) iowrite64be(v, p) |
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| 245 | +#endif |
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| 246 | + |
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| 247 | +#define FSL_DMA_IN(fsl_dma, addr, width) \ |
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| 248 | + (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \ |
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| 249 | + fsl_ioread##width##be(addr) : fsl_ioread##width(addr)) |
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| 250 | + |
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| 251 | +#define FSL_DMA_OUT(fsl_dma, addr, val, width) \ |
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| 252 | + (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \ |
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| 253 | + fsl_iowrite##width##be(val, addr) : fsl_iowrite \ |
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| 254 | + ##width(val, addr)) |
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| 232 | 255 | |
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| 233 | 256 | #define DMA_TO_CPU(fsl_chan, d, width) \ |
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| 234 | 257 | (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ |
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