| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Freescale MPC85xx, MPC83xx DMA Engine support |
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| 3 | 4 | * |
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| .. | .. |
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| 16 | 17 | * command for PCI read operations, instead of using the default PCI Read Line |
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| 17 | 18 | * command. Please be aware that this setting may result in read pre-fetching |
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| 18 | 19 | * on some platforms. |
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| 19 | | - * |
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| 20 | | - * This is free software; you can redistribute it and/or modify |
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| 21 | | - * it under the terms of the GNU General Public License as published by |
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| 22 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 23 | | - * (at your option) any later version. |
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| 24 | | - * |
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| 25 | 20 | */ |
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| 26 | 21 | |
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| 27 | 22 | #include <linux/init.h> |
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| .. | .. |
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| 53 | 48 | |
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| 54 | 49 | static void set_sr(struct fsldma_chan *chan, u32 val) |
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| 55 | 50 | { |
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| 56 | | - DMA_OUT(chan, &chan->regs->sr, val, 32); |
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| 51 | + FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); |
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| 57 | 52 | } |
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| 58 | 53 | |
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| 59 | 54 | static u32 get_sr(struct fsldma_chan *chan) |
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| 60 | 55 | { |
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| 61 | | - return DMA_IN(chan, &chan->regs->sr, 32); |
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| 56 | + return FSL_DMA_IN(chan, &chan->regs->sr, 32); |
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| 62 | 57 | } |
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| 63 | 58 | |
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| 64 | 59 | static void set_mr(struct fsldma_chan *chan, u32 val) |
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| 65 | 60 | { |
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| 66 | | - DMA_OUT(chan, &chan->regs->mr, val, 32); |
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| 61 | + FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); |
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| 67 | 62 | } |
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| 68 | 63 | |
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| 69 | 64 | static u32 get_mr(struct fsldma_chan *chan) |
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| 70 | 65 | { |
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| 71 | | - return DMA_IN(chan, &chan->regs->mr, 32); |
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| 66 | + return FSL_DMA_IN(chan, &chan->regs->mr, 32); |
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| 72 | 67 | } |
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| 73 | 68 | |
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| 74 | 69 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
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| 75 | 70 | { |
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| 76 | | - DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
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| 71 | + FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
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| 77 | 72 | } |
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| 78 | 73 | |
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| 79 | 74 | static dma_addr_t get_cdar(struct fsldma_chan *chan) |
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| 80 | 75 | { |
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| 81 | | - return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
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| 76 | + return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
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| 82 | 77 | } |
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| 83 | 78 | |
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| 84 | 79 | static void set_bcr(struct fsldma_chan *chan, u32 val) |
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| 85 | 80 | { |
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| 86 | | - DMA_OUT(chan, &chan->regs->bcr, val, 32); |
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| 81 | + FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32); |
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| 87 | 82 | } |
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| 88 | 83 | |
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| 89 | 84 | static u32 get_bcr(struct fsldma_chan *chan) |
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| 90 | 85 | { |
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| 91 | | - return DMA_IN(chan, &chan->regs->bcr, 32); |
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| 86 | + return FSL_DMA_IN(chan, &chan->regs->bcr, 32); |
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| 92 | 87 | } |
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| 93 | 88 | |
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| 94 | 89 | /* |
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| .. | .. |
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| 981 | 976 | return IRQ_HANDLED; |
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| 982 | 977 | } |
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| 983 | 978 | |
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| 984 | | -static void dma_do_tasklet(unsigned long data) |
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| 979 | +static void dma_do_tasklet(struct tasklet_struct *t) |
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| 985 | 980 | { |
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| 986 | | - struct fsldma_chan *chan = (struct fsldma_chan *)data; |
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| 981 | + struct fsldma_chan *chan = from_tasklet(chan, t, tasklet); |
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| 987 | 982 | |
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| 988 | 983 | chan_dbg(chan, "tasklet entry\n"); |
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| 989 | 984 | |
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| 990 | | - spin_lock_bh(&chan->desc_lock); |
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| 985 | + spin_lock(&chan->desc_lock); |
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| 991 | 986 | |
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| 992 | 987 | /* the hardware is now idle and ready for more */ |
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| 993 | 988 | chan->idle = true; |
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| .. | .. |
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| 995 | 990 | /* Run all cleanup for descriptors which have been completed */ |
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| 996 | 991 | fsldma_cleanup_descriptors(chan); |
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| 997 | 992 | |
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| 998 | | - spin_unlock_bh(&chan->desc_lock); |
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| 993 | + spin_unlock(&chan->desc_lock); |
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| 999 | 994 | |
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| 1000 | 995 | chan_dbg(chan, "tasklet exit\n"); |
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| 1001 | 996 | } |
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| .. | .. |
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| 1156 | 1151 | } |
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| 1157 | 1152 | |
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| 1158 | 1153 | fdev->chan[chan->id] = chan; |
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| 1159 | | - tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); |
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| 1154 | + tasklet_setup(&chan->tasklet, dma_do_tasklet); |
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| 1160 | 1155 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
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| 1161 | 1156 | |
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| 1162 | 1157 | /* Initialize the channel */ |
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| .. | .. |
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| 1168 | 1163 | switch (chan->feature & FSL_DMA_IP_MASK) { |
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| 1169 | 1164 | case FSL_DMA_IP_85XX: |
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| 1170 | 1165 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
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| 1166 | + fallthrough; |
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| 1171 | 1167 | case FSL_DMA_IP_83XX: |
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| 1172 | 1168 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
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| 1173 | 1169 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; |
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