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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Header file for the Atmel AHB DMA Controller driver |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2008 Atmel Corporation |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License as published by |
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| 8 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 9 | | - * (at your option) any later version. |
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| 10 | 6 | */ |
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| 11 | 7 | #ifndef AT_HDMAC_REGS_H |
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| 12 | 8 | #define AT_HDMAC_REGS_H |
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| .. | .. |
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| 168 | 164 | /* LLI == Linked List Item; aka DMA buffer descriptor */ |
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| 169 | 165 | struct at_lli { |
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| 170 | 166 | /* values that are not changed by hardware */ |
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| 171 | | - dma_addr_t saddr; |
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| 172 | | - dma_addr_t daddr; |
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| 167 | + u32 saddr; |
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| 168 | + u32 daddr; |
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| 173 | 169 | /* value that may get written back: */ |
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| 174 | | - u32 ctrla; |
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| 170 | + u32 ctrla; |
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| 175 | 171 | /* more values that are not changed by hardware */ |
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| 176 | | - u32 ctrlb; |
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| 177 | | - dma_addr_t dscr; /* chain to next lli */ |
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| 172 | + u32 ctrlb; |
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| 173 | + u32 dscr; /* chain to next lli */ |
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| 178 | 174 | }; |
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| 179 | 175 | |
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| 180 | 176 | /** |
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| .. | .. |
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| 247 | 243 | * @active_list: list of descriptors dmaengine is being running on |
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| 248 | 244 | * @queue: list of descriptors ready to be submitted to engine |
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| 249 | 245 | * @free_list: list of descriptors usable by the channel |
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| 250 | | - * @descs_allocated: records the actual size of the descriptor pool |
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| 251 | 246 | */ |
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| 252 | 247 | struct at_dma_chan { |
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| 253 | 248 | struct dma_chan chan_common; |
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| .. | .. |
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| 268 | 263 | struct list_head active_list; |
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| 269 | 264 | struct list_head queue; |
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| 270 | 265 | struct list_head free_list; |
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| 271 | | - unsigned int descs_allocated; |
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| 272 | 266 | }; |
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| 273 | 267 | |
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| 274 | 268 | #define channel_readl(atchan, name) \ |
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| .. | .. |
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| 337 | 331 | struct dma_pool *dma_desc_pool; |
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| 338 | 332 | struct dma_pool *memset_pool; |
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| 339 | 333 | /* AT THE END channels table */ |
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| 340 | | - struct at_dma_chan chan[0]; |
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| 334 | + struct at_dma_chan chan[]; |
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| 341 | 335 | }; |
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| 342 | 336 | |
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| 343 | 337 | #define dma_readl(atdma, name) \ |
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