change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/devfreq/Kconfig
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@@ -1,3 +1,4 @@
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+# SPDX-License-Identifier: GPL-2.0-only
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 menuconfig PM_DEVFREQ
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 	bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
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 	select SRCU
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@@ -76,13 +77,12 @@
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 comment "DEVFREQ Drivers"
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 config ARM_EXYNOS_BUS_DEVFREQ
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-	tristate "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
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+	tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
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 	depends on ARCH_EXYNOS || COMPILE_TEST
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 	select DEVFREQ_GOV_SIMPLE_ONDEMAND
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 	select DEVFREQ_GOV_PASSIVE
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 	select DEVFREQ_EVENT_EXYNOS_PPMU
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 	select PM_DEVFREQ_EVENT
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-	select PM_OPP
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 	help
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 	  This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
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 	  Memory bus has one more group of memory bus (e.g, MIF and INT block).
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@@ -91,15 +91,45 @@
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 	  and adjusts the operating frequencies and voltages with OPP support.
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 	  This does not yet operate with optimal voltages.
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-config ARM_TEGRA_DEVFREQ
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-	tristate "Tegra DEVFREQ Driver"
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-	depends on ARCH_TEGRA_124_SOC
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+config ARM_IMX_BUS_DEVFREQ
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+	tristate "i.MX Generic Bus DEVFREQ Driver"
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+	depends on ARCH_MXC || COMPILE_TEST
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+	select DEVFREQ_GOV_USERSPACE
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+	help
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+	  This adds the generic DEVFREQ driver for i.MX interconnects. It
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+	  allows adjusting NIC/NOC frequency.
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+
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+config ARM_IMX8M_DDRC_DEVFREQ
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+	tristate "i.MX8M DDRC DEVFREQ Driver"
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+	depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
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+		(COMPILE_TEST && HAVE_ARM_SMCCC)
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 	select DEVFREQ_GOV_SIMPLE_ONDEMAND
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-	select PM_OPP
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+	select DEVFREQ_GOV_USERSPACE
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+	help
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+	  This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
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+	  adjusting DRAM frequency.
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+
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+config ARM_TEGRA_DEVFREQ
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+	tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
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+	depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
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+		ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
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+		ARCH_TEGRA_210_SOC || \
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+		COMPILE_TEST
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+	depends on COMMON_CLK
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 	help
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 	  This adds the DEVFREQ driver for the Tegra family of SoCs.
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 	  It reads ACTMON counters of memory controllers and adjusts the
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 	  operating frequencies and voltages with OPP support.
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+
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+config ARM_TEGRA20_DEVFREQ
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+	tristate "NVIDIA Tegra20 DEVFREQ Driver"
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+	depends on (TEGRA_MC && TEGRA20_EMC) || COMPILE_TEST
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+	depends on COMMON_CLK
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+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
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+	help
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+	  This adds the DEVFREQ driver for the Tegra20 family of SoCs.
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+	  It reads Memory Controller counters and adjusts the operating
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+	  frequencies and voltages with OPP support.
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 config ARM_ROCKCHIP_BUS_DEVFREQ
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 	tristate "ARM ROCKCHIP BUS DEVFREQ Driver"
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@@ -109,24 +139,14 @@
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 config ARM_ROCKCHIP_DMC_DEVFREQ
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 	tristate "ARM ROCKCHIP DMC DEVFREQ Driver"
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-	depends on ARCH_ROCKCHIP
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 	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
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 		(COMPILE_TEST && HAVE_ARM_SMCCC)
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 	select DEVFREQ_EVENT_ROCKCHIP_DFI
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 	select PM_DEVFREQ_EVENT
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-	select PM_OPP
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 	help
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 	  This adds the DEVFREQ driver for the ROCKCHIP DMC(Dynamic Memory Controller).
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 	  It sets the frequency for the memory controller and reads the usage counts
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 	  from hardware.
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-
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-config ARM_ROCKCHIP_DMC_DEBUG
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-	tristate "ARM ROCKCHIP DMC DEBUG Driver"
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-	depends on ARCH_ROCKCHIP
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-	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
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-		(COMPILE_TEST && HAVE_ARM_SMCCC)
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-	help
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-	  This adds the dmc debug driver for the ROCKCHIP DMC.
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 source "drivers/devfreq/event/Kconfig"
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