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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/sunxi-ng/ccu-sun8i-r.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3
- *
4
- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk-provider.h>
....@@ -25,10 +17,13 @@
2517 
2618 #include "ccu-sun8i-r.h"
2719 
28
-static const char * const ar100_parents[] = { "osc32k", "osc24M",
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-					     "pll-periph0", "iosc" };
30
-static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M",
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-						   "pll-periph0", "iosc" };
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+static const struct clk_parent_data ar100_parents[] = {
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+	{ .fw_name = "losc" },
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+	{ .fw_name = "hosc" },
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+	{ .fw_name = "pll-periph" },
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+	{ .fw_name = "iosc" },
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+};
26
+
3227 static const struct ccu_mux_var_prediv ar100_predivs[] = {
3328 	{ .index = 2, .shift = 8, .width = 5 },
3429 };
....@@ -47,64 +42,37 @@
4742 	.common		= {
4843 		.reg		= 0x00,
4944 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
50
-		.hw.init	= CLK_HW_INIT_PARENTS("ar100",
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-						      ar100_parents,
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-						      &ccu_div_ops,
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-						      0),
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+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("ar100",
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+							   ar100_parents,
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+							   &ccu_div_ops,
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+							   0),
5449 	},
5550 };
5651 
57
-static struct ccu_div a83t_ar100_clk = {
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-	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
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+static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
5953 
60
-	.mux		= {
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-		.shift	= 16,
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-		.width	= 2,
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+static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
6355 
64
-		.var_predivs	= ar100_predivs,
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-		.n_var_predivs	= ARRAY_SIZE(ar100_predivs),
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-	},
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-
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-	.common		= {
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-		.reg		= 0x00,
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-		.features	= CCU_FEATURE_VARIABLE_PREDIV,
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-		.hw.init	= CLK_HW_INIT_PARENTS("ar100",
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-						      a83t_ar100_parents,
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-						      &ccu_div_ops,
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-						      0),
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-	},
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-};
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-
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-static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
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-
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-static struct ccu_div apb0_clk = {
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-	.div		= _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
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-
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-	.common		= {
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-		.reg		= 0x0c,
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-		.hw.init	= CLK_HW_INIT("apb0",
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-					      "ahb0",
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-					      &ccu_div_ops,
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-					      0),
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-	},
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-};
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-
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-static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
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-
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-static SUNXI_CCU_GATE(apb0_pio_clk,	"apb0-pio",	"apb0",
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-		      0x28, BIT(0), 0);
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-static SUNXI_CCU_GATE(apb0_ir_clk,	"apb0-ir",	"apb0",
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-		      0x28, BIT(1), 0);
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-static SUNXI_CCU_GATE(apb0_timer_clk,	"apb0-timer",	"apb0",
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-		      0x28, BIT(2), 0);
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-static SUNXI_CCU_GATE(apb0_rsb_clk,	"apb0-rsb",	"apb0",
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-		      0x28, BIT(3), 0);
102
-static SUNXI_CCU_GATE(apb0_uart_clk,	"apb0-uart",	"apb0",
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-		      0x28, BIT(4), 0);
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-static SUNXI_CCU_GATE(apb0_i2c_clk,	"apb0-i2c",	"apb0",
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-		      0x28, BIT(6), 0);
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-static SUNXI_CCU_GATE(apb0_twd_clk,	"apb0-twd",	"apb0",
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-		      0x28, BIT(7), 0);
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+/*
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+ * Define the parent as an array that can be reused to save space
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+ * instead of having compound literals for each gate. Also have it
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+ * non-const so we can change it on the A83T.
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+ */
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+static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw };
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+static SUNXI_CCU_GATE_HWS(apb0_pio_clk,		"apb0-pio",
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+			  apb0_gate_parent, 0x28, BIT(0), 0);
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+static SUNXI_CCU_GATE_HWS(apb0_ir_clk,		"apb0-ir",
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+			  apb0_gate_parent, 0x28, BIT(1), 0);
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+static SUNXI_CCU_GATE_HWS(apb0_timer_clk,	"apb0-timer",
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+			  apb0_gate_parent, 0x28, BIT(2), 0);
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+static SUNXI_CCU_GATE_HWS(apb0_rsb_clk,		"apb0-rsb",
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+			  apb0_gate_parent, 0x28, BIT(3), 0);
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+static SUNXI_CCU_GATE_HWS(apb0_uart_clk,	"apb0-uart",
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+			  apb0_gate_parent, 0x28, BIT(4), 0);
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+static SUNXI_CCU_GATE_HWS(apb0_i2c_clk,		"apb0-i2c",
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+			  apb0_gate_parent, 0x28, BIT(6), 0);
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+static SUNXI_CCU_GATE_HWS(apb0_twd_clk,		"apb0-twd",
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+			  apb0_gate_parent, 0x28, BIT(7), 0);
10876 
10977 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
11078 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
....@@ -115,7 +83,10 @@
11583 				  BIT(31),	/* gate */
11684 				  0);
11785 
118
-static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" };
86
+static const struct clk_parent_data a83t_r_mod0_parents[] = {
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+	{ .fw_name = "iosc" },
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+	{ .fw_name = "hosc" },
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+};
11990 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
12091 	{ .index = 0, .div = 16 },
12192 };
....@@ -135,16 +106,16 @@
135106 	.common		= {
136107 		.reg		= 0x54,
137108 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
138
-		.hw.init	= CLK_HW_INIT_PARENTS("ir",
139
-						      a83t_r_mod0_parents,
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-						      &ccu_mp_ops,
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-						      0),
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+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("ir",
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+							   a83t_r_mod0_parents,
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+							   &ccu_mp_ops,
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+							   0),
142113 	},
143114 };
144115 
145116 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
146
-	&a83t_ar100_clk.common,
147
-	&a83t_apb0_clk.common,
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+	&ar100_clk.common,
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+	&apb0_clk.common,
148119 	&apb0_pio_clk.common,
149120 	&apb0_ir_clk.common,
150121 	&apb0_timer_clk.common,
....@@ -182,9 +153,9 @@
182153 
183154 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
184155 	.hws	= {
185
-		[CLK_AR100]		= &a83t_ar100_clk.common.hw,
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+		[CLK_AR100]		= &ar100_clk.common.hw,
186157 		[CLK_AHB0]		= &ahb0_clk.hw,
187
-		[CLK_APB0]		= &a83t_apb0_clk.common.hw,
158
+		[CLK_APB0]		= &apb0_clk.common.hw,
188159 		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
189160 		[CLK_APB0_IR]		= &apb0_ir_clk.common.hw,
190161 		[CLK_APB0_TIMER]	= &apb0_timer_clk.common.hw,