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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (c) 2014 MundoReader S.L.
34  * Author: Heiko Stuebner <heiko@sntech.de>
....@@ -11,16 +12,6 @@
1112  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
1213  * Copyright (c) 2013 Linaro Ltd.
1314  * Author: Thomas Abraham <thomas.ab@samsung.com>
14
- *
15
- * This program is free software; you can redistribute it and/or modify
16
- * it under the terms of the GNU General Public License as published by
17
- * the Free Software Foundation; either version 2 of the License, or
18
- * (at your option) any later version.
19
- *
20
- * This program is distributed in the hope that it will be useful,
21
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
22
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
- * GNU General Public License for more details.
2415  */
2516 
2617 #ifndef CLK_ROCKCHIP_CLK_H
....@@ -86,6 +77,64 @@
8677 #define PX30_PMU_CLKSEL_CON(x)		((x) * 0x4 + 0x40)
8778 #define PX30_PMU_CLKGATE_CON(x)		((x) * 0x4 + 0x80)
8879 #define PX30_PMU_MODE			0x0020
80
+
81
+#define RV1106_TOPCRU_BASE		0x10000
82
+#define RV1106_PERICRU_BASE		0x12000
83
+#define RV1106_VICRU_BASE		0x14000
84
+#define RV1106_NPUCRU_BASE		0x16000
85
+#define RV1106_CORECRU_BASE		0x18000
86
+#define RV1106_VEPUCRU_BASE		0x1A000
87
+#define RV1106_VOCRU_BASE		0x1C000
88
+#define RV1106_DDRCRU_BASE		0x1E000
89
+#define RV1106_SUBDDRCRU_BASE		0x1F000
90
+
91
+#define RV1106_VI_GRF_BASE		0x50000
92
+#define RV1106_VO_GRF_BASE		0x60000
93
+
94
+#define RV1106_PMUCLKSEL_CON(x)		((x) * 0x4 + 0x300)
95
+#define RV1106_PMUCLKGATE_CON(x)	((x) * 0x4 + 0x800)
96
+#define RV1106_PMUSOFTRST_CON(x)	((x) * 0x4 + 0xa00)
97
+#define RV1106_PLL_CON(x)		((x) * 0x4 + RV1106_TOPCRU_BASE)
98
+#define RV1106_MODE_CON			(0x280 + RV1106_TOPCRU_BASE)
99
+#define RV1106_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
100
+#define RV1106_CLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
101
+#define RV1106_SOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
102
+#define RV1106_GLB_SRST_FST		(0xc08 + RV1106_TOPCRU_BASE)
103
+#define RV1106_GLB_SRST_SND		(0xc0c + RV1106_TOPCRU_BASE)
104
+#define RV1106_SDIO_CON0		(0x1c + RV1106_VO_GRF_BASE)
105
+#define RV1106_SDIO_CON1		(0x20 + RV1106_VO_GRF_BASE)
106
+#define RV1106_SDMMC_CON0		(0x4 + RV1106_VI_GRF_BASE)
107
+#define RV1106_SDMMC_CON1		(0x8 + RV1106_VI_GRF_BASE)
108
+#define RV1106_EMMC_CON0		(0x20)
109
+#define RV1106_EMMC_CON1		(0x24)
110
+#define RV1106_PERICLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
111
+#define RV1106_PERICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
112
+#define RV1106_PERISOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
113
+#define RV1106_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
114
+#define RV1106_VICLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
115
+#define RV1106_VISOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
116
+#define RV1106_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
117
+#define RV1106_VICLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
118
+#define RV1106_VISOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
119
+#define RV1106_NPUCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
120
+#define RV1106_NPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
121
+#define RV1106_NPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
122
+#define RV1106_CORECLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
123
+#define RV1106_CORECLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
124
+#define RV1106_CORESOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
125
+#define RV1106_VEPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
126
+#define RV1106_VEPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
127
+#define RV1106_VEPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
128
+#define RV1106_VOCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
129
+#define RV1106_VOCLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
130
+#define RV1106_VOSOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
131
+#define RV1106_DDRCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
132
+#define RV1106_DDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
133
+#define RV1106_DDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
134
+#define RV1106_SUBDDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
135
+#define RV1106_SUBDDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
136
+#define RV1106_SUBDDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
137
+#define RV1106_SUBDDRMODE_CON		(0x280 + RV1106_SUBDDRCRU_BASE)
89138 
90139 #define RV1108_PLL_CON(x)		((x) * 0x4)
91140 #define RV1108_CLKSEL_CON(x)		((x) * 0x4 + 0x60)
....@@ -255,6 +304,73 @@
255304 #define RK3399_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x100)
256305 #define RK3399_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x110)
257306 
307
+#define RK3528_PMU_CRU_BASE		0x10000
308
+#define RK3528_PCIE_CRU_BASE		0x20000
309
+#define RK3528_DDRPHY_CRU_BASE		0x28000
310
+#define RK3528_VPU_GRF_BASE		0x40000
311
+#define RK3528_VO_GRF_BASE		0x60000
312
+#define RK3528_SDMMC_CON0		(RK3528_VO_GRF_BASE + 0x24)
313
+#define RK3528_SDMMC_CON1		(RK3528_VO_GRF_BASE + 0x28)
314
+#define RK3528_SDIO0_CON0		(RK3528_VPU_GRF_BASE + 0x4)
315
+#define RK3528_SDIO0_CON1		(RK3528_VPU_GRF_BASE + 0x8)
316
+#define RK3528_SDIO1_CON0		(RK3528_VPU_GRF_BASE + 0xc)
317
+#define RK3528_SDIO1_CON1		(RK3528_VPU_GRF_BASE + 0x10)
318
+#define RK3528_PLL_CON(x)		RK2928_PLL_CON(x)
319
+#define RK3528_PCIE_PLL_CON(x)		((x) * 0x4 + RK3528_PCIE_CRU_BASE)
320
+#define RK3528_DDRPHY_PLL_CON(x)	((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
321
+#define RK3528_MODE_CON			0x280
322
+#define RK3528_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
323
+#define RK3528_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
324
+#define RK3528_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
325
+#define RK3528_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
326
+#define RK3528_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
327
+#define RK3528_PCIE_CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
328
+#define RK3528_PCIE_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
329
+#define RK3528_DDRPHY_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
330
+#define RK3528_DDRPHY_MODE_CON		(0x280 + RK3528_DDRPHY_CRU_BASE)
331
+#define RK3528_GLB_CNT_TH		0xc00
332
+#define RK3528_GLB_SRST_FST		0xc08
333
+#define RK3528_GLB_SRST_SND		0xc0c
334
+
335
+#define RK3562_PMU0_CRU_BASE		0x10000
336
+#define RK3562_PMU1_CRU_BASE		0x18000
337
+#define RK3562_DDR_CRU_BASE		0x20000
338
+#define RK3562_SUBDDR_CRU_BASE		0x28000
339
+#define RK3562_PERI_CRU_BASE		0x30000
340
+
341
+#define RK3562_PLL_CON(x)		RK2928_PLL_CON(x)
342
+#define RK3562_PMU1_PLL_CON(x)		((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
343
+#define RK3562_SUBDDR_PLL_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
344
+#define RK3562_MODE_CON			0x600
345
+#define RK3562_PMU1_MODE_CON		(RK3562_PMU1_CRU_BASE + 0x380)
346
+#define RK3562_SUBDDR_MODE_CON		(RK3562_SUBDDR_CRU_BASE + 0x380)
347
+#define RK3562_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
348
+#define RK3562_CLKGATE_CON(x)		((x) * 0x4 + 0x300)
349
+#define RK3562_SOFTRST_CON(x)		((x) * 0x4 + 0x400)
350
+#define RK3562_DDR_CLKSEL_CON(x)	((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
351
+#define RK3562_DDR_CLKGATE_CON(x)	((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
352
+#define RK3562_DDR_SOFTRST_CON(x)	((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
353
+#define RK3562_SUBDDR_CLKSEL_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
354
+#define RK3562_SUBDDR_CLKGATE_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
355
+#define RK3562_SUBDDR_SOFTRST_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
356
+#define RK3562_PERI_CLKSEL_CON(x)	((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
357
+#define RK3562_PERI_CLKGATE_CON(x)	((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
358
+#define RK3562_PERI_SOFTRST_CON(x)	((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
359
+#define RK3562_PMU0_CLKSEL_CON(x)	((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
360
+#define RK3562_PMU0_CLKGATE_CON(x)	((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
361
+#define RK3562_PMU0_SOFTRST_CON(x)	((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
362
+#define RK3562_PMU1_CLKSEL_CON(x)	((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
363
+#define RK3562_PMU1_CLKGATE_CON(x)	((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
364
+#define RK3562_PMU1_SOFTRST_CON(x)	((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
365
+#define RK3562_GLB_SRST_FST		0x614
366
+#define RK3562_GLB_SRST_SND		0x618
367
+#define RK3562_GLB_RST_CON		0x61c
368
+#define RK3562_GLB_RST_ST		0x620
369
+#define RK3562_SDMMC0_CON0		0x624
370
+#define RK3562_SDMMC0_CON1		0x628
371
+#define RK3562_SDMMC1_CON0		0x62c
372
+#define RK3562_SDMMC1_CON1		0x630
373
+
258374 #define RK3568_PLL_CON(x)		RK2928_PLL_CON(x)
259375 #define RK3568_MODE_CON0		0xc0
260376 #define RK3568_MISC_CON0		0xc4
....@@ -283,11 +399,58 @@
283399 #define RK3568_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)
284400 #define RK3568_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)
285401 
402
+#define RK3588_PHP_CRU_BASE		0x8000
403
+#define RK3588_PMU_CRU_BASE		0x30000
404
+#define RK3588_BIGCORE0_CRU_BASE	0x50000
405
+#define RK3588_BIGCORE1_CRU_BASE	0x52000
406
+#define RK3588_DSU_CRU_BASE		0x58000
407
+
408
+#define RK3588_PLL_CON(x)		RK2928_PLL_CON(x)
409
+#define RK3588_MODE_CON0		0x280
410
+#define RK3588_B0_PLL_MODE_CON0		(RK3588_BIGCORE0_CRU_BASE + 0x280)
411
+#define RK3588_B1_PLL_MODE_CON0		(RK3588_BIGCORE1_CRU_BASE + 0x280)
412
+#define RK3588_LPLL_MODE_CON0		(RK3588_DSU_CRU_BASE + 0x280)
413
+#define RK3588_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
414
+#define RK3588_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
415
+#define RK3588_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
416
+#define RK3588_GLB_CNT_TH		0xc00
417
+#define RK3588_GLB_SRST_FST		0xc08
418
+#define RK3588_GLB_SRST_SND		0xc0c
419
+#define RK3588_GLB_RST_CON		0xc10
420
+#define RK3588_GLB_RST_ST		0xc04
421
+#define RK3588_SDIO_CON0		0xC24
422
+#define RK3588_SDIO_CON1		0xC28
423
+#define RK3588_SDMMC_CON0		0xC30
424
+#define RK3588_SDMMC_CON1		0xC34
425
+
426
+#define RK3588_PHP_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
427
+#define RK3588_PHP_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
428
+
429
+#define RK3588_PMU_PLL_CON(x)		((x) * 0x4 + RK3588_PHP_CRU_BASE)
430
+#define RK3588_PMU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
431
+#define RK3588_PMU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
432
+#define RK3588_PMU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
433
+
434
+#define RK3588_B0_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
435
+#define RK3588_BIGCORE0_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
436
+#define RK3588_BIGCORE0_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
437
+#define RK3588_BIGCORE0_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
438
+#define RK3588_B1_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
439
+#define RK3588_BIGCORE1_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
440
+#define RK3588_BIGCORE1_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
441
+#define RK3588_BIGCORE1_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
442
+#define RK3588_LPLL_CON(x)		((x) * 0x4 + RK3588_DSU_CRU_BASE)
443
+#define RK3588_DSU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
444
+#define RK3588_DSU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
445
+#define RK3588_DSU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
446
+
286447 enum rockchip_pll_type {
287448 	pll_rk3036,
288449 	pll_rk3066,
289450 	pll_rk3328,
290451 	pll_rk3399,
452
+	pll_rk3588,
453
+	pll_rk3588_core,
291454 };
292455 
293456 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,	\
....@@ -320,12 +483,22 @@
320483 	.nb = _nb,						\
321484 }
322485 
486
+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k)			\
487
+{								\
488
+	.rate	= _rate##U,					\
489
+	.p = _p,						\
490
+	.m = _m,						\
491
+	.s = _s,						\
492
+	.k = _k,						\
493
+}
494
+
323495 /**
324496  * struct rockchip_clk_provider - information about clock provider
325497  * @reg_base: virtual address for the register base.
326498  * @clk_data: holds clock related data like clk* and number of clocks.
327499  * @cru_node: device-node of the clock-provider
328500  * @grf: regmap of the general-register-files syscon
501
+ * @list_node: node in the global ctx list
329502  * @lock: maintains exclusion between callbacks for a given clock-provider.
330503  */
331504 struct rockchip_clk_provider {
....@@ -334,6 +507,7 @@
334507 	struct device_node *cru_node;
335508 	struct regmap *grf;
336509 	struct regmap *pmugrf;
510
+	struct hlist_node list_node;
337511 	spinlock_t lock;
338512 };
339513 
....@@ -355,6 +529,13 @@
355529 			unsigned int postdiv2;
356530 			unsigned int dsmpd;
357531 			unsigned int frac;
532
+		};
533
+		struct {
534
+			/* for RK3588 */
535
+			unsigned int m;
536
+			unsigned int p;
537
+			unsigned int s;
538
+			unsigned int k;
358539 		};
359540 	};
360541 };
....@@ -399,6 +580,7 @@
399580 #define ROCKCHIP_PLL_SYNC_RATE		BIT(0)
400581 /* normal mode only. now only for pll_rk3036, pll_rk3328 type */
401582 #define ROCKCHIP_PLL_FIXED_MODE		BIT(1)
583
+#define ROCKCHIP_PLL_ALLOW_POWER_DOWN	BIT(2)
402584 
403585 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,	\
404586 		_lshift, _pflags, _rtable)				\
....@@ -438,7 +620,7 @@
438620 	u32 val;
439621 };
440622 
441
-#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	5
623
+#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	6
442624 #define ROCKCHIP_CPUCLK_MAX_CORES	4
443625 struct rockchip_cpuclk_rate_table {
444626 	unsigned long prate;
....@@ -453,6 +635,7 @@
453635  * @div_core_shift[]:	cores divider offset used to divide the pll value
454636  * @div_core_mask[]:	cores divider mask
455637  * @num_cores:	number of cpu cores
638
+ * @mux_core_reg:       register offset of the cores select parent
456639  * @mux_core_alt:       mux value to select alternate parent
457640  * @mux_core_main:	mux value to select main parent of core
458641  * @mux_core_shift:	offset of the core multiplexer
....@@ -463,6 +646,7 @@
463646 	u8	div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
464647 	u32	div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
465648 	int	num_cores;
649
+	int	mux_core_reg;
466650 	u8	mux_core_alt;
467651 	u8	mux_core_main;
468652 	u8	mux_core_shift;
....@@ -471,10 +655,22 @@
471655 };
472656 
473657 struct clk *rockchip_clk_register_cpuclk(const char *name,
474
-			const char *const *parent_names, u8 num_parents,
658
+			u8 num_parents,
659
+			struct clk *parent, struct clk *alt_parent,
475660 			const struct rockchip_cpuclk_reg_data *reg_data,
476661 			const struct rockchip_cpuclk_rate_table *rates,
477662 			int nrates, void __iomem *reg_base, spinlock_t *lock);
663
+
664
+struct clk *rockchip_clk_register_cpuclk_v2(const char *name,
665
+					    const char *const *parent_names,
666
+					    u8 num_parents, void __iomem *base,
667
+					    int muxdiv_offset, u8 mux_shift,
668
+					    u8 mux_width, u8 mux_flags,
669
+					    int div_offset, u8 div_shift,
670
+					    u8 div_width, u8 div_flags,
671
+					    unsigned long flags, spinlock_t *lock,
672
+					    const struct rockchip_cpuclk_rate_table *rates,
673
+					    int nrates);
478674 
479675 struct clk *rockchip_clk_register_mmc(const char *name,
480676 				const char *const *parent_names, u8 num_parents,
....@@ -483,11 +679,13 @@
483679 /*
484680  * DDRCLK flags, including method of setting the rate
485681  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
486
- * ROCKCHIP_DDRCLK_SCPI: use SCPI APIs to let mcu change ddrclk rate.
487682  */
488683 #define ROCKCHIP_DDRCLK_SIP		BIT(0)
489
-#define ROCKCHIP_DDRCLK_SCPI		0x02
490684 #define ROCKCHIP_DDRCLK_SIP_V2		0x03
685
+
686
+#ifdef CONFIG_ROCKCHIP_DDRCLK
687
+void rockchip_set_ddrclk_params(void __iomem *params);
688
+void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void));
491689 
492690 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
493691 					 const char *const *parent_names,
....@@ -495,6 +693,20 @@
495693 					 int mux_shift, int mux_width,
496694 					 int div_shift, int div_width,
497695 					 int ddr_flags, void __iomem *reg_base);
696
+#else
697
+static inline void rockchip_set_ddrclk_params(void __iomem *params) {}
698
+static inline void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void)) {}
699
+static inline
700
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
701
+					 const char *const *parent_names,
702
+					 u8 num_parents, int mux_offset,
703
+					 int mux_shift, int mux_width,
704
+					 int div_shift, int div_width,
705
+					 int ddr_flags, void __iomem *reg_base)
706
+{
707
+	return NULL;
708
+}
709
+#endif
498710 
499711 #define ROCKCHIP_INVERTER_HIWORD_MASK	BIT(0)
500712 
....@@ -512,19 +724,18 @@
512724 
513725 enum rockchip_clk_branch_type {
514726 	branch_composite,
515
-	branch_composite_brother,
516727 	branch_mux,
517728 	branch_muxgrf,
518729 	branch_muxpmugrf,
519730 	branch_divider,
520731 	branch_fraction_divider,
521732 	branch_gate,
733
+	branch_gate_no_set_rate,
522734 	branch_mmc,
523735 	branch_inverter,
524736 	branch_factor,
525737 	branch_ddrclk,
526738 	branch_half_divider,
527
-	branch_dclk_divider,
528739 };
529740 
530741 struct rockchip_clk_branch {
....@@ -548,7 +759,6 @@
548759 	u8				gate_shift;
549760 	u8				gate_flags;
550761 	struct rockchip_clk_branch	*child;
551
-	unsigned long			max_prate;
552762 };
553763 
554764 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
....@@ -570,28 +780,6 @@
570780 		.gate_offset	= go,				\
571781 		.gate_shift	= gs,				\
572782 		.gate_flags	= gf,				\
573
-	}
574
-
575
-#define COMPOSITE_BROTHER(_id, cname, pnames, f, mo, ms, mw, mf,\
576
-			  ds, dw, df, go, gs, gf, bro)		\
577
-	{							\
578
-		.id		= _id,				\
579
-		.branch_type	= branch_composite_brother,	\
580
-		.name		= cname,			\
581
-		.parent_names	= pnames,			\
582
-		.num_parents	= ARRAY_SIZE(pnames),		\
583
-		.flags		= f,				\
584
-		.muxdiv_offset	= mo,				\
585
-		.mux_shift	= ms,				\
586
-		.mux_width	= mw,				\
587
-		.mux_flags	= mf,				\
588
-		.div_shift	= ds,				\
589
-		.div_width	= dw,				\
590
-		.div_flags	= df,				\
591
-		.gate_offset	= go,				\
592
-		.gate_shift	= gs,				\
593
-		.gate_flags	= gf,				\
594
-		.child		= bro,				\
595783 	}
596784 
597785 #define COMPOSITE_MUXTBL(_id, cname, pnames, f, mo, ms, mw, mf,	\
....@@ -712,26 +900,6 @@
712900 		.gate_offset	= -1,				\
713901 	}
714902 
715
-#define COMPOSITE_BROTHER_NOGATE(_id, cname, pnames, f, mo, ms, \
716
-				 mw, mf, ds, dw, df, bro)	\
717
-	{							\
718
-		.id		= _id,				\
719
-		.branch_type	= branch_composite_brother,	\
720
-		.name		= cname,			\
721
-		.parent_names	= pnames,			\
722
-		.num_parents	= ARRAY_SIZE(pnames),		\
723
-		.flags		= f,				\
724
-		.muxdiv_offset	= mo,				\
725
-		.mux_shift	= ms,				\
726
-		.mux_width	= mw,				\
727
-		.mux_flags	= mf,				\
728
-		.div_shift	= ds,				\
729
-		.div_width	= dw,				\
730
-		.div_flags	= df,				\
731
-		.gate_offset	= -1,				\
732
-		.child		= bro,				\
733
-	}
734
-
735903 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,	\
736904 				mw, mf, ds, dw, df, dt)		\
737905 	{							\
....@@ -752,7 +920,7 @@
752920 		.gate_offset	= -1,				\
753921 	}
754922 
755
-#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
923
+#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
756924 	{							\
757925 		.id		= _id,				\
758926 		.branch_type	= branch_fraction_divider,	\
....@@ -767,10 +935,9 @@
767935 		.gate_offset	= go,				\
768936 		.gate_shift	= gs,				\
769937 		.gate_flags	= gf,				\
770
-		.max_prate	= prate,			\
771938 	}
772939 
773
-#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
940
+#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
774941 	{							\
775942 		.id		= _id,				\
776943 		.branch_type	= branch_fraction_divider,	\
....@@ -786,10 +953,9 @@
786953 		.gate_shift	= gs,				\
787954 		.gate_flags	= gf,				\
788955 		.child		= ch,				\
789
-		.max_prate	= prate,			\
790956 	}
791957 
792
-#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
958
+#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
793959 	{							\
794960 		.id		= _id,				\
795961 		.branch_type	= branch_fraction_divider,	\
....@@ -803,7 +969,6 @@
803969 		.div_flags	= df,				\
804970 		.gate_offset	= -1,				\
805971 		.child		= ch,				\
806
-		.max_prate	= prate,			\
807972 	}
808973 
809974 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw,	\
....@@ -919,6 +1084,19 @@
9191084 	{							\
9201085 		.id		= _id,				\
9211086 		.branch_type	= branch_gate,			\
1087
+		.name		= cname,			\
1088
+		.parent_names	= (const char *[]){ pname },	\
1089
+		.num_parents	= 1,				\
1090
+		.flags		= f,				\
1091
+		.gate_offset	= o,				\
1092
+		.gate_shift	= b,				\
1093
+		.gate_flags	= gf,				\
1094
+	}
1095
+
1096
+#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf)	\
1097
+	{							\
1098
+		.id		= _id,				\
1099
+		.branch_type	= branch_gate_no_set_rate,	\
9221100 		.name		= cname,			\
9231101 		.parent_names	= (const char *[]){ pname },	\
9241102 		.num_parents	= 1,				\
....@@ -1073,28 +1251,6 @@
10731251 		.gate_offset	= -1,				\
10741252 	}
10751253 
1076
-#define COMPOSITE_DCLK(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
1077
-		  df, go, gs, gf, prate)				\
1078
-	{							\
1079
-		.id		= _id,				\
1080
-		.branch_type	= branch_dclk_divider,		\
1081
-		.name		= cname,			\
1082
-		.parent_names	= pnames,			\
1083
-		.num_parents	= ARRAY_SIZE(pnames),		\
1084
-		.flags		= f,				\
1085
-		.muxdiv_offset	= mo,				\
1086
-		.mux_shift	= ms,				\
1087
-		.mux_width	= mw,				\
1088
-		.mux_flags	= mf,				\
1089
-		.div_shift	= ds,				\
1090
-		.div_width	= dw,				\
1091
-		.div_flags	= df,				\
1092
-		.gate_offset	= go,				\
1093
-		.gate_shift	= gs,				\
1094
-		.gate_flags	= gf,				\
1095
-		.max_prate	= prate,				\
1096
-	}
1097
-
10981254 /* SGRF clocks are only accessible from secure mode, so not controllable */
10991255 #define SGRF_GATE(_id, cname, pname)				\
11001256 		FACTOR(_id, cname, pname, 0, 1, 1)
....@@ -1112,12 +1268,17 @@
11121268 				struct rockchip_pll_clock *pll_list,
11131269 				unsigned int nr_pll, int grf_lock_offset);
11141270 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
1115
-			unsigned int lookup_id, const char *name,
1116
-			const char *const *parent_names, u8 num_parents,
1117
-			const struct rockchip_cpuclk_reg_data *reg_data,
1118
-			const struct rockchip_cpuclk_rate_table *rates,
1119
-			int nrates);
1120
-void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
1271
+				  unsigned int lookup_id,
1272
+				  const char *name,
1273
+				  u8 num_parents,
1274
+				  struct clk *parent, struct clk *alt_parent,
1275
+				  const struct rockchip_cpuclk_reg_data *reg_data,
1276
+				  const struct rockchip_cpuclk_rate_table *rates,
1277
+				  int nrates);
1278
+void rockchip_clk_register_armclk_v2(struct rockchip_clk_provider *ctx,
1279
+				     struct rockchip_clk_branch *list,
1280
+				     const struct rockchip_cpuclk_rate_table *rates,
1281
+				     int nrates);
11211282 int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate);
11221283 int rockchip_pll_clk_scale_to_rate(struct clk *clk, unsigned int scale);
11231284 int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel);
....@@ -1137,21 +1298,6 @@
11371298 					  u8 gate_flags, unsigned long flags,
11381299 					  spinlock_t *lock);
11391300 
1140
-struct clk *rockchip_clk_register_dclk_branch(const char *name,
1141
-					      const char *const *parent_names,
1142
-					      u8 num_parents,
1143
-					      void __iomem *base,
1144
-					      int muxdiv_offset, u8 mux_shift,
1145
-					      u8 mux_width, u8 mux_flags,
1146
-					      int div_offset, u8 div_shift,
1147
-					      u8 div_width, u8 div_flags,
1148
-					      struct clk_div_table *div_table,
1149
-					      int gate_offset,
1150
-					      u8 gate_shift, u8 gate_flags,
1151
-					      unsigned long flags,
1152
-					      unsigned long max_prate,
1153
-					      spinlock_t *lock);
1154
-
11551301 #ifdef CONFIG_RESET_CONTROLLER
11561302 void rockchip_register_softrst(struct device_node *np,
11571303 			       unsigned int num_regs,
....@@ -1165,4 +1311,25 @@
11651311 #endif
11661312 extern void (*rk_dump_cru)(void);
11671313 
1314
+#if IS_MODULE(CONFIG_COMMON_CLK_ROCKCHIP)
1315
+int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
1316
+			 unsigned int *clocks, unsigned int nclocks);
1317
+void rockchip_clk_unprotect(void);
1318
+void rockchip_clk_disable_unused(void);
1319
+#else
1320
+static inline int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
1321
+				       unsigned int *clocks,
1322
+				       unsigned int nclocks)
1323
+{
1324
+	return -EOPNOTSUPP;
1325
+}
1326
+
1327
+static inline void rockchip_clk_unprotect(void)
1328
+{
1329
+}
1330
+
1331
+static inline void rockchip_clk_disable_unused(void)
1332
+{
1333
+}
1334
+#endif
11681335 #endif