forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk-rk3568.c
....@@ -1068,13 +1068,13 @@
10681068 			RK3568_CLKGATE_CON(20), 8, GFLAGS),
10691069 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
10701070 			RK3568_CLKGATE_CON(20), 9, GFLAGS),
1071
-	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1071
+	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
10721072 			RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
10731073 			RK3568_CLKGATE_CON(20), 10, GFLAGS),
1074
-	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1074
+	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
10751075 			RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
10761076 			RK3568_CLKGATE_CON(20), 11, GFLAGS),
1077
-	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
1077
+	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
10781078 			RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
10791079 			RK3568_CLKGATE_CON(20), 12, GFLAGS),
10801080 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
....@@ -1618,6 +1618,16 @@
16181618 	}
16191619 }
16201620 
1621
+static int protect_clocks[] = {
1622
+	ACLK_VO,
1623
+	HCLK_VO,
1624
+	ACLK_VOP,
1625
+	HCLK_VOP,
1626
+	DCLK_VOP0,
1627
+	DCLK_VOP1,
1628
+	DCLK_VOP2,
1629
+};
1630
+
16211631 static void __init rk3568_pmu_clk_init(struct device_node *np)
16221632 {
16231633 	struct rockchip_clk_provider *ctx;
....@@ -1695,6 +1705,8 @@
16951705 
16961706 	if (!rk_dump_cru)
16971707 		rk_dump_cru = rk3568_dump_cru;
1708
+
1709
+	rockchip_clk_protect(ctx, protect_clocks, ARRAY_SIZE(protect_clocks));
16981710 }
16991711 
17001712 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);